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參數(shù)資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 9/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
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Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
9
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high when there are
no twisted-pair cable ports receiving incoming bias (i.e., they are
either disconnected or suspended), and can be used along with LPS
to determine when to power-down the PDI1394P24. The CNA
output is not debounced. When the PD terminal is asserted high, the
CNA detection circuitry is enabled (regardless of the previous state
of the ports) and a pull-down is activated on the RESET terminal so
as to force a reset of the PDI1394P24 internal logic.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC is used in conjunction with the LCtrl bit (see Table 1
and Table 2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY-LLC
interface (the state of the PHY-LCC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).
The LPS input is considered inactive if it remains low for more than
2.6
μ
s
and is considered active otherwise. When the
PDI1394P24
detects that LPS is inactive, it will place the PHY-LLC interface into a
low-power reset state in which the CTL and D outputs are held in the
logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for
more than
26
μ
s, the PHY–LLC interface is put into a low–power
disabled state in which the SYSCLK output is also held inactive. The
PHY–LLC interface is also held in the disabled state during
hardware reset. The
PDI1394P24
will continue the necessary
repeater functions required for normal network operation regardless
of the state of the PHY–LLC interface. When the interface is in the
reset or disabled state and LPS is again observed active, the PHY
will initialize the interface and return it to normal operation.
The PHY uses the C/LKON terminal to notify the LLC to power up
and become active. When activated, the C/LKON signal is a square
wave of approximately
163
ns period. The PHY activates the
C/LKON output when the LLC is inactive and a wake–up event
occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrI bit is cleared to 0. A
wake–up event occurs when a link–on PHY packet addressed to
this node is received, or conditionally when a PHY interrupt occurs.
The PHY deasserts the C/LKON output when the LLC becomes
active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus–reset occurs unless a
PHY interrupt condition exists which would otherwise cause
C/LKON to be active.
8.0
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
MIN
MAX
V
DD
V
I
V
I
–5V
V
O
DC supply voltage
–0.5
4.0
V
DC input voltage
–0.5
V
DD
+0.5
5.5
V
5 volt tolerant input voltage range
–0.5
V
DC output voltage range at any output
–0.5
V
DD
+0.5
2
V
Electrostatic discharge
Human Body Model
kV
Machine Model
200
V
T
amb
T
stg
Operating free-air temperature range
0
+70
°
C
°
C
Storage temperature range
–65
+150
NOTE:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
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