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參數(shù)資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
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Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
6
Name
Description
I/O
Pin Numbers
Pin Type
R0, R1
Bias
54, 55
—
Current setting resistor terminals. These terminals are connected to
an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 6.34 k
±
1% is required to
meet the IEEE Std 1394–1995 output voltage limits.
SYSCLK
CMOS
63
O
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
TEST0
CMOS
29
I
Test control input. This input is used in manufacturing tests of the
PDI1394P24. For normal use, this terminal should be tied to GND.
TEST1
CMOS
28
I
Test control input. This input is used in manufacturing tests of the
PDI1394P24. For normal use, this terminal should be tied to GND.
TPA0+,
TPA1+
Cable
36, 41
I/O
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector. TPA+ and TPA– can be left unconnected on an
unused port.
TPA0–,
TPA1–
Cable
35, 40
I/O
TPB0+,
TPB1+
Cable
34, 39
I/O
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector. TPB+ and TPB– should be tied together and pulled
to ground on an unused port.
TPB0–,
TPB1–
Cable
33, 38
I/O
TPBIAS0,
TPBIAS1
Cable
37, 42
I/O
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a
0.3
μ
F–1
μ
F capacitor to ground. TPBIAS can be left unconnected on an
unused port.
XO, XI
Crystal
60, 59
—
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case). For more information, refer to
Section 17.5.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
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