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參數(shù)資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 26/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
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Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
26
18.3
Whenever the PHY detects the data-prefix state on the serial bus, it
initiates a receive operation by asserting Receive on the CTL terminals
and a logic 1 on each of the D terminals (“data-on” indication). The
PHY indicates the start of a packet by placing the speed code
(encoded as shown in Table 19) on the D terminals, followed by
packet data. The PHY holds the CTL terminals in the Receive state
until the last symbol of the packet has been transferred. The PHY
indicates the end of packet data by asserting Idle on the CTL
terminals. All received packets are transferred to the LLC. Note that
the speed code is part of the PHY-LLC protocol and is not included in
the calculation of CRC or any other data protection mechanisms.
Receive
Table 19. Speed Code for the Receiver
D0–D7
DATA RATE
0000 0000
S100
0100 0000
S200
0101 0000
S400
1111 1111
“data-on” indication
It is possible for the PHY to receive a null packet, which consists of
the data-prefix state on the serial bus followed by the data-end state,
without any packet data. A null packet is transmitted whenever the
packet speed exceeds the capability of the receiving PHY, or
whenever the LLC immediately releases the bus without transmitting
any data. In this case, the PHY will assert Receive on the CTL
terminals with the “data-on” indication (all 1’s) on the D terminals,
followed by Idle on the CTL terminals, without any speed code or
data being transferred. In all cases, in normal operation, the
PDI1394P24 sends at least one “data-on” indication before sending
the speed code or terminating the receive operation.
The PDI1394P24 also transfers its own self-ID packet, transmitted
during the self-ID phase of bus initialization to the LLC. This packet
is transferred to the LLC just as any other received self-ID packet.
The sequence of events for a normal packet reception is as follows:
Receive operation initiated. The PHY indicates a receive
operation by asserting Receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
progress so that the CTL lines may change from status to receive
without an intervening idle.
Data-on indication. The PHY may assert the data-on indication code
on the D lines for one or more cycles preceding the speed code.
Speed code. the PHY indicates the speed of the received packet
by asserting a speed code on the D lines for one cycle
immediately preceding packet data. The link decodes the speed
code on the first Receive cycle for which the D lines are not the
data-on code. If the speed code is invalid, or indicates a speed
higher than that which the link is capable of handling, the link
should ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the
speed code, the PHY asserts packet data on the D lines with
receive on the CTL lines for the remainder of the receive operation.
Receive operation terminated. The PHY terminates the receive
operation by asserting the idle on the CTL lines. The PHY asserts
at least one cycle of idle following a receive operation.
SYSCLK
(a)
(b)
CTL0, CTL1
D0–D7
XX
00
00
10
00
01
dn
FF (“data-on”)
SV01760
(e)
d0
SPD
(c)
(d)
NOTE:
SPD = Speed code; see Table 19; d0–dn = Packet data.
Figure 15.
Normal Packet Reception Timing
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| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
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| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
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