- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367854 > PDI1394P24 (NXP Semiconductors N.V.) 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) PDF資料下載
參數(shù)資料
| 型號(hào)： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 21/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
21
node–to–node communication paths that pass through the local
node’s PHY will be restricted by the lower speed.
In the case of a leaf node (which has only one active port) the
Link_Speed field may be set to indicate the speed of the LLC
without first checking the speed–map. Changing the Link_Speed
field in a leaf node can only affect those paths that terminate at that
node, since no other paths can pass through a leaf node. It can
have no effect on other paths in the speed–map. For hardware
configurations which can only be a leaf node (all ports but one are
unimplemented), it is recommended that the Link_Speed field be
updated immediately after power–on or hardware reset.
17.5
The PDI1394P24 is designed to use an external 24.576 MHz crystal
connected between the XI and XO terminals to provide the
reference for an internal oscillator circuit. This oscillator in turn
drives a PLL circuit that generates the various clocks required for
transmission and resynchronization of data at the S100 through
S400 media data rates.
Crystal selection
A variation of less than
±
100 ppm from nominal for the media data
rates is required by IEEE Std 1394. Adjacent PHYs may therefore
have a difference of up to 200 ppm from each other in their internal
clocks, and PHYs must be able to compensate for this difference
over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted
packet data.
For the PDI1394P24, the SYSCLK output may be used to measure
the frequency accuracy and stability of the internal oscillator and
PLL from which it is derived. The frequency of the SYSCLK output
must be within
±
100 ppm of the nominal frequency of 49.152 MHz.
The following are some typical specifications for crystals used with
the PDI1394P24 in order to achieve the required frequency
accuracy and stability:
Crystal mode of operation: Fundamental
Frequency tolerance at 25
°
C: Total frequency variation for the
complete circuit is +100 ppm. A crystal with +30 ppm frequency
tolerance is recommended for adequate margin.
Frequency stability (over temperature and age): A crystal with +30
ppm frequency stability is recommended for adequate margin.
NOTE: The total frequency variation must be kept below
±
100 ppm
from nominal with some allowance for error introduced by board and
device variations. Trade–offs between frequency tolerance and
stability may be made as long as the total frequency variation is less
than
±
100 ppm. For example, the frequency tolerance of the crystal
may be specified at 50 ppm and the temperature tolerance may be
specified at 30 ppm to give a total of 80 ppm possible variation due
to the crystal alone. Crystal aging also contributes to the frequency
variation.
Load capacitance: For parallel resonant mode crystal circuits, the
frequency of oscillation is dependent upon the load capacitance
specified for the crystal. Total load capacitance (C
L
) is a function
of not only the discrete load capacitors, but also board layout and
circuit. It may be necessary to iteratively select discrete load
capacitors until the SYSCLK output is within specification. It is
recommended that load capacitors with a maximum of
tolerance be used.
5%
As an example, for a board which uses a crystal specified for 12 pF
loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each
are appropriate for the layout of that particular board. The load
specified for the crystal includes the load capacitors (C9, C10), the
loading of the PHY terminals (C
PHY
), and the loading of the board
itself (C
BD
). The value of C
PHY
is typically about 1 pF, and C
BD
is
typically 0.8 pF per centimeter of board etch; a typical board can
have 3 pF to 6 pF or more. The load capacitors C9 and C10
combine as capacitors in series so that the total load capacitance is:
C
L
= [(C9 *
C10) / (C9+C10)] + C
PHY
+ C
BD
.
SV01808
C9
24.576 MHz
C10
XI
XO
ls
X1
C
PHY
+ C
BD
Figure 10.
Load Capacitance for the PDI1394P24 PHY
NOTE: The layout of the crystal portion of the PHY circuit is
important for obtaining the correct frequency, minimizing noise
introduced into the PHY’s Phase Lock Loop, and minimizing any
emissions from the circuit. The crystal and two load capacitors
should be considered as a unit during layout. The crystal and load
capacitors should be placed as close as possible to one another
while minimizing the loop area created by the combination of the
three components. Varying the size of the capacitors may help in
this. Minimizing the loop area minimizes the effect of the resonant
current (Is) that flows in this resonant circuit. This layout unit (crystal
and load capacitors) should then be placed as close as possible to
the PHY XI and XO terminals to minimize trace lengths.
SV01809
C9
C10
X1
Figure 11.
Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for
the design be to measure the frequency of the SYSCLK output of
the PHY. This should be done with a frequency counter with an
accuracy of 6 digits or better. If the SYSCLK frequency is more than
the crystal’s tolerance from 49.152 MHz, the load capacitance of the
crystal may be varied to improve frequency accuracy. If the
frequency is too high add more load capacitance; if the frequency is
too low decrease load capacitance. Typically, changes should be
done to both load capacitors (C9 and C10 above) at the same time,
and both should be of the same value. Additional design details and
requirements may be provided by the crystal vendor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI40C1D00 | |
| PDI40C1300 | |
| PDI40C130R | |
| PDI40C130X | |
| PDI40C13R0 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。