參數(shù)資料
型號(hào)： PDI1394P24
廠商： NXP Semiconductors N.V.
英文描述： 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口)
中文描述： 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口）
文件頁(yè)數(shù)： 36/39頁(yè)
文件大小： 188K
代理商： PDI1394P24
Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
36
CTL lines and the data–on indication (all ones) on the D lines for
one or more cycles.
4. Initialization complete. The PHY asserts the Idle state on the
CTL lines and logic 0 on the D lines. This indicates that the
PHY–LLC interface initialization is complete and normal
operation may commence. The PHY will now accept requests
from the LLC via the LREQ line.
19.0
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted
self-ID packet. Descriptions of the various power-classes are given in Table 21. The default power-class value is loaded following a hardware
reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4.
POWER-CLASS PROGRAMMING
Table 21. Power Class Descriptions
PC0–PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self powered, and provides a minimum of 15 W to the bus.
010
Node is self powered, and provides a minimum of 30 W to the bus.
011
Node is self powered, and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W.
101
Node is powered from the bus and uses up to 3 W. No additional power is needed to enable the link.
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
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