參數(shù)資料
型號(hào)： PDI1394P24
廠商： NXP Semiconductors N.V.
英文描述： 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口)
中文描述： 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口）
文件頁(yè)數(shù)： 34/39頁(yè)
文件大?。?/td> 188K
代理商： PDI1394P24
Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
34
The sequence of events for disabling the PHY–LLC interface when it
is in the non–differentiated mode of operation (ISO terminal is high)
is as follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via the
LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high–impedance state, and drives
its LREQ output low.
3. Interface reset. After T
LPS_RESET
time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and drives
its CTL and D outputs low. The PHY–LLC interface is now in the
reset state.
4. Interface disabled. If the LPS signal remain inactive for
T
LPS_DISABLE
time, the PHY terminates SYSCLK activity by
driving the SYSCLK output low. The PHY–LLC interface is now
in the disabled state.
After the interface has been reset, or reset and then disabled, the
interface is initialized and restored to normal operation when LPS is
reasserted by the LLC. The timing for interface initialization is shown
in Figure 23 and Figure 24.
T
CLK_ACTIVATE
CTL0
LPS
SV01814
ISO
SYSCLK
D0 – D7
LREQ
(low)
(c)
7 cycles
5 ns. min
10 ns. max
(d)
(b)
CTL1
(a)
Figure 23.
Interface Initialization, ISO Low
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