21
User’s Manual U14701EJ3V0UD
LIST OF FIGURES (5/7)
Figure No.
Title
Page
14-10
Receive Error Timing ...........................................................................................................................
255
15-1
Serial Interface SIO3 Block Diagram ...................................................................................................
256
15-2
Serial Operation Mode Register 3 (CSIM3) Format.............................................................................
259
15-3
Timing of 3-Wire Serial I/O Mode ........................................................................................................
263
16-1
Serial Interface CSI1 Block Diagram....................................................................................................
265
16-2
Serial Operation Mode Register 1 (CSIM1) Format.............................................................................
266
16-3
Serial Clock Select Register 1 (CSIC1) Format ...................................................................................
267
16-4
Timing in 3-Wire Serial I/O Mode.........................................................................................................
272
16-5
Timing of Clock/Data Phase ................................................................................................................
274
16-6
Output Operation of First Bit ................................................................................................................
275
16-7
Output Value of SO1 Pin (Last Bit).......................................................................................................
276
17-1
LCD Controller/Driver Block Diagram ..................................................................................................
280
17-2
LCD Display Mode Register 3 (LCDM3) Format..................................................................................
282
17-3
Blinking Function..................................................................................................................................
283
17-4
LCD Clock Control Register 3 (LCDC3) Format ..................................................................................
284
17-5
Relationship Between Reference Clock Generating Frame Frequency, and Frame Frequency ..........
285
17-6
Static/Dynamic Display Switching Register 3 (SDSEL3) Format.........................................................
286
17-7
Pin Function Switching Registers 8 and 9 (PF8 and PF9) Format ......................................................
287
17-8
Relationship Between LCD Display Data, Contents of Blinking Select Bits,
and Segment/Common Output Signals (4-Time Division) ...................................................................
288
17-9
Common Signal Waveform ..................................................................................................................
291
17-10
Common Signal and Segment Signal Voltages and Phases ...............................................................
292
17-11
Example of Circuit to Adjust LCD Driver Reference Voltage................................................................
293
17-12
Static LCD Panel Display Pattern and Electrode Connections ............................................................
295
17-13
Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1) ........................................................
296
17-14
Static LCD Drive Waveform Examples.................................................................................................
297
17-15
3-Time-Division LCD Display Pattern and Electrode Connections ......................................................
298
17-16
3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2) .....................................
299
17-17
3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................................................
300
17-18
4-Time-Division LCD Display Pattern and Electrode Connections ......................................................
301
17-19
4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2) .....................................
302
17-20
4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...................................................
303
18-1
Basic Configuration of Interrupt Function ............................................................................................
307
18-2
Interrupt Request Flag Registers (IF0L, IF0H, IF1L) Format ...............................................................
310
18-3
Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) Format .............................................................
311
18-4
Priority Specification Flag Registers (PR0L, PR0H, PR1L) Format.....................................................
312