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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U14701EJ3V0UD
Figure 6-2. 16-Bit Timer Mode Control Register 0 (TMC0) Format
TMC03
TMC02
TMC01
Operation mode and
clear mode selection
TO0 output timing selection
Interrupt request generation
0
0
0
Operation stop
No change
Not generated
0
0
1
(TM0 cleared to 0)
0
1
0
Free-running mode
Match between TM0 and
CR00 or match between TM0
and CR01
0
1
1
Match between TM0 and
CR00, match between TM0
and CR01 or TI00 valid edge
1
0
0
Clear & start on TI00 valid
—
1
0
1
edge
1
1
0
Clear & start on match
between TM0 and CR00
Match between TM0 and
CR00 or match between TM0
and CR01
1
1
1
Match between TM0 and
CR00, match between TM0
and CR01 or TI00 valid edge
OVF0
16-bit timer counter 0 (TM0) overflow detection
0
Overflow not detected
1
Overflow detected
Cautions 1. Be sure to stop timer operation before writing to bits other than the OVF0 flag.
2. Set the valid edge of the TI00/P31 pin with prescaler mode register 0 (PRM0).
3. If clear & start mode on match between TM0 and CR00 is selected, when the set value of
CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set to 1.
Remarks 1.
TO0:
16-bit timer/event counter 0 output pin
16-bit timer/event counter 0 input pin
16-bit timer counter 0
4.
CR00: 16-bit timer capture/compare register 00
5.
CR01: 16-bit timer capture/compare register 01
2.
TI00:
3.
TM0:
Generated on match
between TM0 and CR00, or
match between TM0 and
CR01
7
0
6
0
5
0
4
0
3
TMC03
2
TMC02
1
TMC01
0
OVF0
Symbol
TMC0
Address: FF60H After reset: 00H R/W