20
User’s Manual U14701EJ3V0UD
LIST OF FIGURES (4/7)
Figure No.
Title
Page
11-3
Port Mode Register 0 (PM0) Format....................................................................................................
209
11-4
Remote Control Output Application Example ......................................................................................
210
12-1
A/D Converter Block Diagram ..............................................................................................................
211
12-2
A/D Converter Mode Register 0 (ADM0) Format .................................................................................
214
12-3
Analog Input Channel Specification Register 0 (ADS0) Format ..........................................................
215
12-4
External Interrupt Rising Edge Enable Register (EGP),
External Interrupt Falling Edge Enable Register (EGN) Format ..........................................................
215
12-5
Basic Operation of A/D Converter........................................................................................................
217
12-6
Relationship Between Analog Input Voltage and A/D Conversion Result ............................................
218
12-7
A/D Conversion by Hardware Start (When Falling Edge Is Specified).................................................
220
12-8
A/D Conversion by Software Start .......................................................................................................
221
12-9
Overall Error.........................................................................................................................................
222
12-10
Quantization Error................................................................................................................................
222
12-11
Zero Scale Error...................................................................................................................................
223
12-12
Full Scale Error ....................................................................................................................................
223
12-13
Integral Linearity Error .........................................................................................................................
223
12-14
Differential Linearity Error ....................................................................................................................
223
12-15
Example of Method of Reducing Current Consumption in Standby Mode...........................................
225
12-16
Analog Input Pin Connection ...............................................................................................................
226
12-17
A/D Conversion End Interrupt Request Generation Timing .................................................................
227
12-18
Timing of Reading Conversion Result (When Conversion Result Is Undefined) .................................
228
12-19
Timing of Reading Conversion Result (When Conversion Result Is Normal) ......................................
228
12-20
Example of Connecting Capacitor to V
DD1
and AV
REF0
Pins.................................................................
229
12-21
Internal Equivalent Circuit of ANI0 to ANI9 Pins ..................................................................................
230
12-22
Example of Connection If Signal Source Impedance Is High ..............................................................
230
13-1
D/A Converter Block Diagram ..............................................................................................................
232
13-2
D/A Converter Mode Register 0 (DAM0) Format .................................................................................
233
13-3
Buffer Amp Insertion Example .............................................................................................................
235
14-1
Serial Interface UART0 Block Diagram ................................................................................................
237
14-2
Baud Rate Generator Block Diagram ..................................................................................................
237
14-3
Asynchronous Serial Interface Mode Register 0 (ASIM0) Format .......................................................
240
14-4
Asynchronous Serial Interface Status Register 0 (ASIS0) Format ......................................................
241
14-5
Baud Rate Generator Control Register 0 (BRGC0) Format.................................................................
242
14-6
Baud Rate Error Tolerance (When k = 0), Including Sampling Errors..................................................
250
14-7
Format of Transmit/Receive Data in Asynchronous Serial Interface ....................................................
251
14-8
Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request...............................
253
14-9
Timing of Asynchronous Serial Interface Receive Completion Interrupt Request ...............................
254