參數(shù)資料
型號(hào): NCN6804MNR2G
廠商: ON Semiconductor
文件頁(yè)數(shù): 9/25頁(yè)
文件大?。?/td> 0K
描述: IC SMART CARD DUAL W/SPI 32-QFN
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: 智能卡
接口: 4 線 SPI 串行
電源電壓: 2.7 V ~ 5.5 V
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 剪切帶 (CT)
安裝類型: 表面貼裝
其它名稱: NCN6804MNR2GOSCT
NCN6804
http://onsemi.com
17
Table 7. INTERRUPT RESET LOGIC TABLE
Interrupt Source
(INT set to LOW)
CS
Interrupt Clearance (INT reset to HIGH) CRD_VCCA/B / {b1, b0} pro-
gramming
Chip Address
Card Insertion
L
{0,1}, {1,0} or {11}
{b7:b5} = 0XX
Card Extraction
L
{0,0}
{b7:b5} = 0XX
Over Load
L
{0,0}
{b7:b5} = 0XX
In order to know the source of the interrupt (card A or card
B), the software has to poll the MISO register by sending a
MOSI A command (address {b7, b6, b5} = {0, X, 0})
followed by a MOSI B command (address {b7, b6, b5} = {0,
X, 1}) (or conversely). The corresponding MISO content
provides the previous state of the interface A or B that is the
information related to the cause of the interrupt. For each
case the MISO status obtained will be compared with the
MISO state prior to the interrupt. When 2 NCN6804 devices
share the same digital SPI bus, it is up to the software to poll
the devices using again the MISO register to identify the
reason of the interrupt.
Figure 10. Basic Interrupt Function
CS
INT
CRD_DET
MOSI_b0
MOSI_b1
CRD_VCC > 0 V
OVER LOAD
CRD_VCC
T0
T2
T10
T3
T4
T9
T6
T8
T5
T1
T11
T12
T7
{b1,b0} = {0,1}, {1,0} or {1,1}
{b1,b0} = {0,0}
CRD_VCC > 0 V
Table 8. INTERRUPT FUNCTION OPERATION
T0
A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line.
T1
The mC sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register.
T2
The mC acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T3
The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the
PWR_DOWN sequence is activated by the NCN6001.
T4
The interrupt pin is clear by the zero volt programmed to the interface.
T5
Same as T0
T6
The mC start the DC/DC converter, the interrupt is cleared (same as T2)
T7
An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low.
T8
The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L).
T9
The card is reinserted before the interrupt is acknowledged by the mC: the INT pin stays Low.
T10
The mC acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
T11
The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or
transaction can take place.
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