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參數(shù)資料
| 型號(hào)： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 7/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
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NCN6804
http://onsemi.com
15
Figure 6. Figure 7: Start Up Sequence with ATR.
Powerdown Sequence
The NCN6804 provides an automatic Power Down
sequence, according to the ISO78163 specifications. When
a power down sequence is enabled the communication
session terminates immediately. The sequence is launched
under a microcontroller decision, when the card is
extracted, or when the CRD_VCCA/B voltage is overloaded
as described by the ISO/CEI 78163 sequence depicted here
after (see Figure 8):
CRD_ RST is forced to Low
CRD_CLK is forced to Low, unless it is already in this
state
CRD_C4 & CRD_C8 are forced to Low
Then CRD_IO is forced to Low
Finally the CRD_VCC supply is powered down
Figure 7. Typical Power Down Sequence
(Typical Delay Between Each Signal is 500 ns)
CRD_RST
CRD_VCC
CRD_I/O
CRD_C4
CRD_CLK
Since the internal digital filter is activated for any card
insertion or extraction, the physical powerdown sequence
will be activated 50
ms (typical) after the card has been
extracted. Of course, such a delay does not exist when the
microcontroller intentionally launches the power down.
Data I/O Level Shifter
The level shifter accommodates the voltage difference
that might exist between the microcontroller and the smart
card. A pulsed accelerator circuit provides the fast positive
going transient according to the ISO78163 specifications.
The basic I/O level shifter is depicted Figure 8.
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