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參數(shù)資料
| 型號： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
NCN6804
http://onsemi.com
10
PROGRAMMING
Write Register " WRT_REG (Is Low Only)
Similar to the NCN6001, the NCN6804’s WRT_REG register handles 3 command bits [b5:b7] and 5 data bits [b0:b4] as
depicted in Tables 1 and 2. These bits are concatenated into 1 byte [MSB0,LSB0] in order to accelerate the programming
sequence. The register can be updated when CS is low only.
The WRT_RGT has been defined to be compatible with the NCN6001 write register.
Table 1. WRT_REG BIT DEFINITIONS
b0
b1
If (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then
Case 00
CRD_VCCA = 0 V
Case 01
CRD_VCCA = 1.8 V
Case 10
CRD_VCCA = 3.0 V
Case 11
CRD_VCCA = 5.0 V
Else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then
Case 00
CRD_VCCB = 0 V
Case 01
CRD_VCCB = 1.8 V
Case 10
CRD_VCCB = 3.0 V
Case 11
CRD_VCCB = 5.0 V
Else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then
b1 drives CRD_C4A or B (respectively)
b0 drives CRD_C8A or B (respectively)
Else if (b7 + b6 + b5) =101 then
Case 00
CRD_DET = NO
Case 01
CRD_DET = NC
Case 10
SPI_MODE = Special
Case 11
SPI_MODE = Normal
Else if (b7 + b6 + b5) =100 then
NA (Not Applicable)
End if
8. When operating in Asynchronous mode, b6 is compared with the external voltage level present pin S1 (Pin 1).
9. The CRD_RST pin reflects the content of the MOSI WRT_REG [b4] during the chip programming sequence. Since the bit shall be Low
to address the chip’s internal register, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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