參數(shù)資料
型號： NCN6804MNR2G
廠商： ON Semiconductor
文件頁數(shù)： 11/25頁
文件大小： 0K
描述： IC SMART CARD DUAL W/SPI 32-QFN
標準包裝： 1
應(yīng)用： 智能卡
接口： 4 線 SPI 串行
電源電壓： 2.7 V ~ 5.5 V
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 剪切帶 (CT)
安裝類型： 表面貼裝
其它名稱： NCN6804MNR2GOSCT
NCN6804
http://onsemi.com
19
Figure 13. Basic Multi Command SPI Bytes
Select Chip from SYNCHRONOUS Bank
Chip Ny
Chip Nx
tdclk
Special Mode: MISO
is synchronized with
the SPI_CLK Positive
going slope
Normal Mode: MISO is synchronized with
the SPI_CLK Negative going slope
MISO Line = High Impedance
B0
B1
B2
B3
B4
B5
B6
B7
B0
B1
B2
B3
B4
B5
B6
B7
SPI_CLK
CS
MOSI
SET_RST
SET_CLK
SET_VCC
ADDRESS
DECODE
CHIP
ADDRESS
COMMAND
AND CONTROL
MSB
LSB
MISO
Special Mode
MISO
Normal Mode
MPU Enables
Clock
Since the 2 dual circuits present in the Asynchronous
Bank have an individual physical address, the system can
control 2 of these chips by sending the data content within
the same CS frame as depicted in Figure 13. The bits are
decoded on the fly and the related sub blocks are updated
accordingly. According to the SPI general specification, no
code or activity will be transferred to any chip when the CS
is High.
When 2 SPI dual bytes are sequentially transferred on the
MOSI line, the CLK_SPI sequence must be separated by at
least one half positive period of this clock (see tdclk
parameter).
The oscillograms given Figures 14 and 15 illustrate the
SPI communication protocol.
Figure 14. Programming Sequence
Special mode
Standard mode
Figure 15. MISO Read Out Sequences
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