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參數(shù)資料
| 型號(hào)： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
NCN6804
http://onsemi.com
23
CRD_CLK
CLOCK_IN
CLOCK : 2
CLOCK : 4
B2
B3
Clock is updated upon
These bits program
Internal
CLOCK programming is activated
by the B2 + B3 logic state
CLOCK = 1:1 ratio
CLOCK : 1
Figure 22. Typical Clock Divider Synchronization
CLOCK: 4 rising edge
CLOCK
Divider
In order to avoid any duty cycle out of the smart card
ISO78163 specification, the divider is synchronized by the
last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio (see Figure 22). Consequently,
the output CRD_CLKA/B frequency division can be
delayed by four CLOCK_IN pulses and the micro controller
software must take this delay into account prior to launch a
new data transaction. On the other hand, the output signal
Duty Cycle cannot be guaranteed 50% if the division ratio
is 1 and if the input Duty Cycle signal is not within the 46%
– 56% range.
The input signals CLK_IN and MOSI/b3 are
automatically routed to the level shifter and control block
according to the mode of operation.
Figure 23. Basic Clock Divider and Level Shifter
B1
B0
B3
B2
CLK_IN
VCC
CRD_CLK
CRD_VCC
LEVEL SHIFTER
AND CONTROL
Programming
CRD_CLK Slope
NOTE: Bits [B0...B3] come from SPI data
Programming
CRD_CLK
Division
SYNC
ASYNC
SYNC
U1
DIGITAL_MUX
OUT
SEL
A
B
The input clock can be divided by 1/1,
, or ,, depending
upon the specific application, prior to be applied to the smart
card driver. On the other hand, the positive and negative
going slopes of the output clock (CRD_CLKA/B) can be
programmed to optimize the operation of the chip: see
Table 2. The slope of the output clock can be programmed
on the fly, independently of either the CRD_VCCA/B
voltage or the operating frequency, but cares must be
observed as the CRD_RSTA/B will reflect the logic state
present at MOSI / b4 register.
Table 9. Output Clock Rise and Fall Time Selection
B0
B1
CRD_CLK
Division Ratio
CRD_CLK
SLO_SLP
CRD_CLK
FST_SLP
0
Output Clock = Low
0
1
10 ns (typ.)
2 ns (typ.)
1
0
1/2
10 ns (typ.)
2 ns (typ.)
1
1/4
10 ns (typ.)
2 ns (typ.)
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