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參數(shù)資料
| 型號： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
NCN6804
http://onsemi.com
12
Table 2. WRT_REG BIT DEFINITIONS AND FUNCTIONS
ADRESS
PARAMETERS
MSB0
LSB0
MOSI bits[
b3 : b2]
MOSI bits
[b1 : b0 ]
MOSI bits
[b3 : b0 ]
b7
b6
b5
b4
b3
b2
b1
b0
CRD_CLK
CRD_VCC
0
S1
A/B
CRD_RST
0
Low
0
S1
A/B
CRD_RST
0
1
0
1
1/1
1.8V
0
S1
A/B
CRD_RST
1
0
1
0
1/2
3.0V
0
S1
A/B
CRD_RST
1
1/4
5.0V
1
A/B
CRD_RST
CRD_CLK
CRD_I/O
CRD_C4
CRD_C8
Synchronous
1
0
1
X
0
NO
1
0
1
X
0
1
NC
1
0
1
X
0
1
0
Special
1
0
1
X
0
1
Normal
1
0
1
X
1
0
SLO_SLP
1
0
1
X
1
0
1
FST_SLP
10.Card A: b5 = 0, Card B: b5 = 1, Device # 1: b6 = 0 pin S1 connected to GND, Device # 2: b6 = 1 pin S1 connected to VDD
11. Address 101 and bits [b0:b4] not documented in the table are not applicable with no effect on the device programming and configuration.
The sign X in the table means that either 1 or 0 can be used.
Read Register READ_REG
The READ_REG register (1 byte) contains the data read
from the card interface. The selected chip register is
transferred to the MISO Pin during the MOSI sequence
(CS = Low).
Table 3 gives a definition of the bits.
Depending upon the programmed SPI_MODE, the
content of READ_REG is transferred on the MISO line
either on the Positive going (SPI_MODE = Special) or upon
the Negative going slope (SPI_MODE = Normal) of the
CLK_SPI signal.
The external microcontroller shall discard the three high
bits since they carry no valid data.
Table 3. MOSI AND MISO BITS IDENTIFICATIONS AND FUNCTIONS
MOSI
b7
b6
b5
b4
b3
b2
b1
b0
Operating Mode
.
0
1
0
1
0
1
0
1
0
1
CRD_RST
CRD_CLK
CRD_I/O
CRD_VCC
CRD_C4
CRD_VCC
CRD_C8
Async. Card A, Program Chip
Async. Card B, Program Chip
Async. Card A, Program Chip
Async. Card B, Program Chip
Sync. Card A, Sets Card Bits
Sync. Card B, Sets Card Bits
MISO
z
Card Detect
CRD_I/O
CRD_C4
CRD_C8
PWR Monitor
Read Back Data
When a command is sent to A for example by selecting the
address %000 the corresponding MISO byte has the state of
the interface A (Card detectA, b4; I/OA, b3; C4A, b2; C8A,
b1; CRD_VCCA ok, b0) – that is the state loaded while
sending the previous MOSI command A or B.
When a command is sent to B for example by selecting the
address %001 the corresponding MISO byte has the state of
the interface B (Card detectB, b4; I/OB, b3; C4B, b2; C8B,
b1; CRD_VCCB ok, b0) – that is the state loaded while
sending the previous MOSI command A or B.
Card A or Card B Selection Multiplexed Mode
The bit b5 in the MOSI sequence enables the selection of
the NCN6804’s interface A or B (see Table 2) to the
exception of the addresses {100} decoded with no effect on
the device and {101} used to program device general
configuration. Then:
When b5 = LOW the interface A is selected and the
transaction or communication takes place through this
interface according to Table 2. The programming applies to
Card A only.
When b5 = HIGH the interface B is selected and the
transaction or communication takes place through this
interface according to Table 1. The programming applies to
Card B only.
CRD_VCCA and CRD_CLKA can be maintained
applied to card A when the device is switched from A to B.
This mode of operating is of course the same when the
device is switched from B to A: CRD_VCCB and
CRD_CLKB can be maintained applied to card B.
The device configuration is programmed using the
address {101} similarly to the NCN6001. In that case, the
programming is applied simultaneously to Card A and
Card B.
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