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參數(shù)資料
| 型號(hào)： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 5/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
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NCN6804
http://onsemi.com
13
Asynchronous Mode
In this mode, the S1 pin is used to define the physical
address (by comparison with the bit b6 (MOSI)) of the
interfaces when a bank of up to 2 NCN6804 (total of 4
interfaces) shares the same digital bus.
Synchronous Mode
In this mode, the CLK_IN clock input and the I/O
input/output are not used. The clock and the data are
provided and transferred through the SPI bus using MOSI
and MISO as shown Table 2.
When this operating mode is used and if two NCN6804
devices want to be implemented, it is no longer possible to
share the same CS signal. Consequently in this particular
case and when the devices operate in a multiple interface
mode a dedicated CS signal must be provided to each
NCN6804 device.
Since bits [b4 – b0] of the MOSI register contain the smart
card data, programming the CRD_VCC output voltage shall
be done by sending a previous MOSI message according to
Table 2 using the address [b7, b6, b5] = [0, S1, A/B]. For
example if a synchronous card is used, prior to make a
transaction with it, it will be poweredup for example at 5
V by sending the command %00000011 (address S1 = 0 and
card A selected).
The CRD_RSTA/B pin reflects the content of the MOSI
WRT_REG [b4] during the chip programming sequence.
Since this bit shall be LOW to address the internal register
of the chip, care must be observed as this signal will be
immediately transferred tot he CRD_RSTA/B pin.
Startup Default Conditions
At startup, when power supply is turned on, the internal
POR (Power On Reset) circuit sets the chip in the default
conditions as defined below (Table 4).
Table 4. STARTUP DEFAULT CONDITIONS
CRD_DETA/B
Normally Open
CRD_VCCA/B
OFF
CRD_CLKA/B
tr & tf = SLOW
CRD_CLKA/B
LOW
Protocol
Special Mode
I/O Pullup resistor
Connected
INT
High
Card Detection
The card is detected by the external switch connected to
pin 23 for Card B and pin 2 for Card A. The internal circuit
provides a positive bias of this pin and the polarity of the
insertion/extraction is programmable by the MOSI protocol
as depicted Table 2.
The bias current is 1
mA typical and cares must be observed
to avoid leakage to ground from this pin to maintain the logic
function. In particular, using a low impedance probe (< 1
M
W) might lead to uncontrolled operation during the debug.
Depending upon the programmed condition, the card can
be detected either by a Normally Open (default condition) or
a Normally Close switch (see Table 2). On the other hand,
the meaning of the feedback message contained in the MISO
register bit b4 depends upon the SPI mode of operation as
defined here below:
SPI Normal Mode: the MISO bit b4 is High when a card is
inserted, whatever be the polarity of the card detect switch.
SPI Special Mode: the MISO bit b4 copies the logic state of
the Card detect switch as depicted here below, whatever be
the polarity of the switch used to handle the detection:
CRD_DETA/B = Low
MISO / b4 = LOW
CRD_DETA/B = High
MISO / b4 = HIGH
CRD_VCC Operation
The dual NCN6804 interface has 2 builtin DC/DC
converters. Each of them can be programmed to provide one
of the three possible values, 1.8 V, 3.0 V or 5.0 V, assuming
the input voltage VDDPA or B is within the 2.7 V to 5.5 V
range. Card A and Card B can be independently poweredup
or down. Consequently if necessary for example the device
can be switched from card A to card B while the card A
power voltage is maintained (this is of course true from A to
B or from B to A). CRD_VCCA & B are voltage regulated
and protected against overload by a current overload
detection system. The DC/DC converter operates as a
buck/boost converter. The power conversion mode is
automatically switched to handle one of these two modes of
operation depending upon the voltage difference between
the CRD_VCCA or B and VDDPA or B respectively.
The CRD_VCCA or B output current range is given
Table 5; these values comply with the smart card ISO7816
standard and related.
Table 5. CRD_VCCA OR B OUTPUT VOLTAGE
DEFINITION
CRD_VCCA or B
Current range
per Card
Cumulated Cur-
rent Range (Card
A and Card B)
1.8 V
0 to 35+ mA
0 to 70 + mA
3.0 V
0 to 60+ mA
0 to 120 + mA
5.0 V
0 to 65+ mA
0 to 130 + mA
Whatever is the CRD_VCCA or B output voltage, a
builtin comparator makes sure the voltage is within the
ISO78163/EMV specifications. If the voltage is no longer
within the minimum/maximum values, the DC/DC is
switched off, the powerdown sequence takes place and an
interrupt is presented at the INT Pin 24.
Powerup Sequence
The Powerup Sequence makes sure all the card related
signals are Low during the CRD_VCCA/B positive going
slope. These lines are validated when CRD_VCCA/B is
above the minimum voltage specified by the EMV standard
depending upon the programmed CRD_VCC A or B value
(see CRD_VCC Power Supply section on page NO TAG).
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