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參數(shù)資料
| 型號： | NCN6004AFTBR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 25/40頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SAM/SIM DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | PC，PDA |
| 接口： | 微控制器 |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6004AFTBR2GOSDKR |
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NCN6004A
http://onsemi.com
31
Figure 31. Parallel Operation Wiring
" MUX_MODE = Low
13
10
11
12
9
19
18
17
16
15
RESET_A
C4_A
C8_A
CLK_IN_A
I/O_A
I/O_B
C8_B
C4_B
RESET_B
CLK_IN_B
44
5
MUX_MODE
CARD_SEL
BUFFERS
BUFFER
I/O_A
BUFFER
I/O_B
CARD_B
CARD_A
CLK_A
CLK_B
23
22
21
24
37
38
39
40
30
31
CLOCK GEN.
MULTIPLEX &
CLOCK DIVIDER
CARD
GND
LOGIC
CONTROL
POR
T
A
POR
T
B
CTL
MICRO
CONTROLLER
When the chip operates in the parallel mode, all the logic
signals
must
be
independently
controlled
by
the
microcontroller as depicted in Figure 31. The MUX_MODE
pin must be hardwired to VCC and it cannot be changed
during an operation of the chip. Beside this parameter, the
user must select to force or not the internal pull up resistors
as defined by the EN_RPU logic state.
Figure 32. Multiplexed Operation Wiring
" MUX_MODE = High
13
10
11
12
9
19
18
17
16
15
RESET_A
C4_A
C8_A
CLK_IN_A
I/O_A
I/O_B
C8_B
C4_B
RESET_B
CLK_IN_B
44
5
MUX_MODE
CARD_SEL
BUFFERS
BUFFER
I/O_A
BUFFER
I/O_B
CARD_B
CARD_A
CLK_A
CLK_B
23
22
21
24
37
38
39
40
30
31
CLOCK GEN.
POR
T
A
POR
T
B
CTL
MICRO
CONTROLLER
MULTIPLEX &
CLOCK DIVIDER
CARD
VCC
LOGIC
CONTROL
In the multiplexed mode, the microprocessor CARD_B
side pins are not connected, the logic signals and the I/O line
being shared with CARD_A associated with the CRD_SEL
control bit: Figure 32. A key point is to make sure there is no
connection associated with the I/O_B pin since this pin is
internally shared with the I/O line transaction. The
CLK_IN_A and CLK_IN_B signals are independent and
can be routed to any of the card thanks to the builtin clock
multiplexer.
DATA I/O LEVEL SHIFTER
The built in structure provides a level shifter on each card
output signals, the I/O line being driven differently as
depicted in Figure 33. Since the NCN6004A can operate in
either a multiplexed or parallel mode, provisions have been
made to route the I/O_A input pin to either CARD_A or
CARD_B.
In both case, the I/O pins are driven by an open drain
structure with a 20 k
W pull up resistor as shown Figure 33.
To achieve the 0.80
ms maximum rise time requested by the
EMV specifications, an accelerator circuit is added on both
side of each I/O line. These pulsed circuits yield boost
current to charge the stray capacitance, thus accelerating the
positive going slope of the I/O signal. On the other hand, the
active pull down NMOS device Q5 provides a low
impedance to ground during the battery up and DC/DC
startup phase, avoiding any uncontrolled voltage spikes on
the I/O lines.
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| NCN6010DTB | 功能描述:轉(zhuǎn)換 - 電壓電平 2.7V Sim Card RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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