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參數(shù)資料
| 型號： | NCN6004AFTBR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SAM/SIM DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | PC，PDA |
| 接口： | 微控制器 |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6004AFTBR2GOSDKR |
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NCN6004A
http://onsemi.com
27
CLOCK DIVIDER
The main purpose of the built in clock generator is four
folds:
1. Adapts the voltage level shifter to cope with the
different voltages that might exist between the
MPU and the Smart Card
2. Provides a frequency division to adapt the Smart
Card operating frequency from the external clock
source.
3. Control the clock state according to the smart card
specification.
4. Provides an input clock rerouting to route the
CLOCK_IN_A and CLOCK_IN_B signals to
either CRD_CLK_A or CRD_CLK_B output pins.
In addition, the NCN6004A adjusts the signal coming
from the microprocessor to get the Duty Cycle window as
defined by the ISO78163 specification.
The logic input pins CARD_SEL, A0, A1, PGM, I/O and
RESET fulfill the programming functions when both PGM
and CS are Low. The clock input stage (CLOCK_IN) can
handle a 40 MHz frequency maximum, the divider being
capable to provide an 1:8 ratio. Of course, the ratio must be
defined by the engineer to cope with the Smart Card
considered in a given application and, in any case, the output
clock (CRD_CLK_A and CRD_CLK_B) shall be limited to
20 MHz maximum when the system is considered to operate
over the full temperature range.
A2
A0
A1
PGM
CS
CLOCK_IN_B
1
2
3
CRD_CLK_A
LEVEL SHIFTER
& CONTROL
CRD_VCC_A
CARD_A & CARD_B CLOCK
CRD_VCC_A
A2
CARD_SEL
CRD_CLK_B
LEVEL SHIFTER
& CONTROL
CRD_VCC_B
CARD_A
CARD_B
DC/DC BLOCK_A
CRD_VCC_B
DC/DC BLOCK_B
CLOCK_IN_A
CLOCK_A
DIVIDER
CLOCK_AB
DIVIDER
MUX_A&B
LOGIC
CONTROL
Figure 24. Simplified Frequency Divider and Programming Functions
In order to avoid any duty cycle out of the frequency smart
card ISO78163 and EMV specifications, the clock divider
is synchronized by the last flip flop, thus yielding a constant
50%
duty
cycle,
regardless
of
the
divider
ratio.
Consequently, the output CRD_CLK_A or CRD_CLK_B
frequency division can be delayed by eight CLOCK_IN
pulses and the microcontroller software must take this delay
into account prior to launch a new data transaction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCN6010 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter |
| NCN6010/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter |
| NCN6010_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter |
| NCN6010D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter |
| NCN6010DTB | 功能描述:轉(zhuǎn)換 - 電壓電平 2.7V Sim Card RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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