參數(shù)資料
型號： NCN6004AFTBR2G
廠商： ON Semiconductor
文件頁數(shù)： 15/40頁
文件大?。?/td> 0K
描述： IC INTERFACE SAM/SIM DUAL 48TQFP
標準包裝： 1
應用： PC，PDA
接口： 微控制器
電源電壓： 1.8 V ~ 5.5 V
封裝/外殼： 48-TQFP 裸露焊盤
供應商設備封裝： 48-TQFP（7x7）
包裝： 標準包裝
安裝類型： 表面貼裝
其它名稱： NCN6004AFTBR2GOSDKR
NCN6004A
http://onsemi.com
22
PWR_ON
tpwrhold
tpwrlow
CARD_SEL
SET
RESET
tpwrpre
tpwrset
tpwrp
NOTE:
tpwrset: This delay is necessary to latch–up the PWR_ON condition
and does not represent the CRD_VCC output voltage rise time.
tpwrlow: This delay includes the internal ISO78163 power down
sequence to make sure the DC/DC converter is fully deactivated.
Figure 13. Power On Sequence Timings
CS
PWR_ON
tpgmdly
CARD_SEL
tcseldly
tpwrw
Programming
Chip Selected
tpwrhold
NOTE:
tpwrw: This delay represents the minimum pulse width needed
to write the PWR_ON status into the associated DC/DC latch
Figure 14. Power On and CARD_SEL Sequence Timings
Sequence
CS
PGM
DC/DC CONVERTER
The power conversion is carried out either in step up or
step down mode. The operation is fully automatic and,
beside the output voltage programming, does not need any
further adjustments.
The simplified DC/DC converter, given in Figure 15, is
based on a full bridge structure capable to handle either step
up or step down power supply using an external inductor.
This structure brings the capability to operate from a wide
range of input voltage, while providing the accurate 1.80 V,
3.0 V or 5.0 V requested by the smart cards. Beside the
accuracy, the major aim of this structure is the high
efficiency necessary to save energy taken from the battery.
On the other hand, using two independent converters
provides a high flexibility and prevent a total system crash
in the event of a failure on one of the card connected to the
interface.
OPERATION
NOTE:
Described operation makes reference to
CARD_A and can be applied to CARD_B.
The system operates with a two cycles concept:
1. Cycle 1: Q15 and Q4 are switched ON and the
inductor L1 is charged by the energy supplied by
the external battery. During this phase, the pairs
Q1/Q16 and Q2/Q3 are switched OFF.
The current flowing into the two MOSFET Q1 and
Q4 is internally monitored and will be switched OFF
when the Ipeak value (depending upon the
programmed output voltage value) is reached. At
this point, Cycle 1 is completed and Cycle 2 takes
place. The ON time is a function of the battery
voltage and the value of the inductor network (L and
Zr) connected across pins 26/27 and 34/35.
A 4
ms time out structure makes sure the system does
run in a continuous Cycle 1 loop.
2. Cycle 2: Q1 and Q16 are switched ON and the
energy stored into the inductor L1 is dumped into
the external load through Q16. During this phase,
the pair Q15/Q4 and the pair Q2/Q3 are switched
OFF.
The current flow period is constant (900 ns typical)
and Cycle 1 repeats after this time if the CRD_VCC
voltage is below the specified value.
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