參數(shù)資料
型號(hào): NCN6004AFTBR2G
廠商: ON Semiconductor
文件頁(yè)數(shù): 21/40頁(yè)
文件大?。?/td> 0K
描述: IC INTERFACE SAM/SIM DUAL 48TQFP
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: PC,PDA
接口: 微控制器
電源電壓: 1.8 V ~ 5.5 V
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
安裝類型: 表面貼裝
其它名稱: NCN6004AFTBR2GOSDKR
NCN6004A
http://onsemi.com
28
CRD_CLK
CLOCK_IN
CLOCK : 2
CLOCK : 4
CLOCK : 8
A0
A1
A2
A3
Clock is updated upon CLOCK :8 rising edge
These
bits
program
Internal
CLOCK
divider
CLOCK programming is activated
by the PGM rising edge.
CLOCK
=
1:1
ratio
CARD_SEL
Figure 25. Clock Programming Timings
CS
PGM
The example given in Figure 25 highlights the delay
coming
from
the
internal
clock
duty
cycle
resynchronization. Since the clock signal is asynchronous,
it is up to the programmer to make sure the next card
transaction is not activated before, respectively, either the
CRD_CLK_A or CRD_CLK_B signal has been updated.
Generally speaking, such a delay can be derived from the
maximum
clock
frequency
provided
to
the
interface.
Figure 26. Card Clock 1/2 Divider Operation
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