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Contents-1
Contents
Chapter 1
Overview
1.1.
Features .................................................................................................................................1-2
1.2.
Block Diagram ......................................................................................................................1-4
1.3.
Pins........................................................................................................................................1-5
1.3.1.
Pin Descriptions...............................................................................................................1-6
1.3.2.
Pin Structure ..................................................................................................................1-11
1.3.3.
Pin Treatment ................................................................................................................1-12
Chapter 2
CPU
2.1.
Overview ...............................................................................................................................2-2
2.2.
CPU Operating States............................................................................................................2-2
2.3.
Switching State......................................................................................................................2-2
2.4.
Memory Formats ...................................................................................................................2-2
2.5.
Instruction Length .................................................................................................................2-3
2.6.
Data Types ............................................................................................................................2-3
2.7.
Operating Modes ...................................................................................................................2-3
2.8.
Registers................................................................................................................................2-4
2.8.1.
The ARM state register set ..............................................................................................2-4
2.8.2.
The Thumb state register set............................................................................................2-6
2.8.3.
The relationship between ARM and Thumb state registers .............................................2-7
2.8.4.
Accessing Hi registers in Thumb state.............................................................................2-7
2.9.
The Program Status Registers ...............................................................................................2-8
2.9.1.
The condition code flags..................................................................................................2-8
2.9.2.
The control bits................................................................................................................2-8
2.10. Exceptions ...........................................................................................................................2-10
2.10.1. Action on entering an exception ....................................................................................2-10
2.10.2. Action on leaving an exception......................................................................................2-11
2.10.3. Exception entry/exit summary .......................................................................................2-11
2.10.4. FIQ.................................................................................................................................2-12
2.10.5. IRQ ................................................................................................................................2-12
2.10.6. Software interrupt ..........................................................................................................2-12
2.10.7. Undefined instruction ....................................................................................................2-12
2.10.8. Exception vectors ..........................................................................................................2-13
2.10.9. Exception priorities........................................................................................................2-13
2.11. Reset....................................................................................................................................2-14
Chapter 3
CPU Control Functions
3.1.
Overview ...............................................................................................................................3-2
3.1.1.
Pins ..................................................................................................................................3-3
3.1.2.
Control Registers .............................................................................................................3-3
3.2.
Detailed Control Register Descriptions.................................................................................3-4
3.2.1.
Standby Control Register (SBYCON) .............................................................................3-4
3.2.2.
Clock Control Register (CKCON)...................................................................................3-5
3.2.3.
Clock Supply Wait Control Register (CKWTCON)........................................................3-6
3.2.4.
Reset Status Register (RSTST)........................................................................................3-7
3.3.
System Resets........................................................................................................................3-8
3.3.1.
Resetting with External Input ..........................................................................................3-8
3.3.2.
Resetting with Watchdog Timer Overflow ......................................................................3-8
3.4.
System Clock (SYSCLK)......................................................................................................3-9