- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4052 > MC68MH360ZQ33L (Freescale Semiconductor)IC MPU QUICC 33MHZ 357-PBGA PDF資料下載
參數(shù)資料
| 型號： | MC68MH360ZQ33L |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 78/158頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當(dāng)前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
QMC Supplement
1.7 SCC Changes on the Fly
Changes can be made on the y in the QMC routing tables, but changes made in the SI
RAM require the link to be disconnected. If the connection is maintained during changes,
synchronization and routing errors are likely to happen in the current frame. A workaround
uses a shadow RAM routing table. The shadow table can hold alternative routing
information to be switched in at the appropriate time slot boundary. The drawback to this
method is that the number of entries in the SI RAM is reduced by half. But since the routing
tables in the QMC protocol are being changed anyway, the recommended solution is to
have all relevant time slots routed to the SCC.
The SI RAM also gives the user the capability to multiplex other channels to and from a
TDM if not all time slots are used by the QMC. A third option is to have several external
devices multiplexed. Use the open collector mode if several QUICCs or PowerQUICCs are
connected together for subchanneling applications.
1.8 SI RAM Errors
The following three types of errors are identied:
Data bit error
Clock pulse error
Synchronization pulse error
Errors in frame-based protocols are easy to detect by the protocol controller. An error in an
HDLC channel is detected at the end of a frame when a buffer is closed and all status bits
are reported in the buffer descriptor (BD). The error type for bit errors is normally CRC
errors. For errors occurring in the SI (noise on clock or synchronization pulses), the error
may also be of type frame-length-violation or non-octet-aligned. See Chapter 5, “Buffer
Descriptors,” for more information. This section covers the type of errors reported through
the buffer descriptors. For transparent channels, the error detection mechanism is left to the
user in higher-level software. Most transparent channels, such as voice carriers, are tolerant
of errors. Frame-based channels, on the other hand, require error detection since they often
rely on critical control messages.
The number of clocks that occur between sync pulses is given in the SI RAM programming.
The clock-counting state machine expects a new sync pulse after the end of each frame. The
following paragraphs discuss the different error cases and describe the counter state and the
frame delay before synchronization is resumed.
A clock pulse error occurs if other than exactly one clock pulse is detected by the SI RAM
in a given frame. In this error case, since the SI RAM bases its routing on counting clock
pulses, the now corrupted signal routing affects all channels. The SI RAM expects another
sync pulse when it reaches the last entry of the frame.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FMC43DRXH-S734 | CONN EDGECARD 86POS DIP .100 SLD |
| FMC36DRYS-S93 | CONN EDGECARD 72POS .100 DIP SLD |
| MC68MH360VR33L | IC MPU QUICC 33MHZ 357-PBGA |
| FMM43DSES-S243 | CONN EDGECARD 86POS .156 EYELET |
| FSM44DSEF-S243 | CONN EDGECARD 88POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68MH360ZQ33LR2 | 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68P11E1CFN2R2 | 制造商:Rochester Electronics LLC 功能描述:8BIT MCU 512RAM A/D EE - Bulk |
| MC68P11E1CFNE2R | 功能描述:8位微控制器 -MCU 8B MCU 512 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68P-3-2 | 制造商:PARKER 功能描述: |
| MC-68PLCC | 制造商:SPC Multicomp 功能描述:SOCKET PLCC 68 PIN THRU-HOLE 制造商:SPC Multicomp 功能描述:SOCKET, PLCC, 68 PIN, THRU-HOLE 制造商:PRIVATE LABEL 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of C 制造商:SPC Multicomp 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of Contacts:68, Pitch Spacing:1.27mm, Contact Termination:Through Hole Vertical, Contact Material:Phosphor Bronze, Contact Plating:Tin , RoHS Compliant: Yes |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。