參數(shù)資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 45/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
Figure C-2. IDL and SCP Connections between the QUICC32 and the S/T Interface
The QUICC32 is always a slave on the IDL bus, with the data clock (DCL) and frame sync
(FSC) signals acting as inputs. As explained in Section C.3, “Data Clock (DCL) and Frame
Sync (FSC) Generation,” this specic application requires the S/T interface be congured
in slave mode on the IDL bus, with external circuitry providing the DCL and FSC signals
to both the QUICC32 and the S/T interface.
The D channel request/grant function is not required for this application since each S/T is
assumed to be directly connected to the NT1 (that is, point-to-point conguration with only
one TE connected to one NT).
The DGNT signal is left unconnected, and DREQ can be directly connected to VSS. As
there is no contention on the D channel, the D channel contention procedure of the
MC145574 should be disabled by setting BR7[6].
Figure C-3 shows the connection between the QUICC32 and a U interface.
ISDN
S/T chip
MC145574
QUICC32
DCL
DIN
DOUT
FSC
DREQ
DGNT
IRQ
SCPEN
L1CLKx
L1TXDx
L1RXDx
L1SYNC
IRQ
GPI/O
SPICLK
SPITX
SPIRX
SCPCLK
SCPRX
SCPTX
Line
Interface
NC
VSS
TE/NT
M/S
GND
VCC
Pull-up resistors on SCPEN and IRQ signals
are not represented.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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