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| 型號(hào)： | MC68MH360ZQ33L |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 133/158頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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QMC Supplement
Figure 5-4 shows a TXB interrupt generated after (PAD + 1) ag characters following the
closing ag. Four ags (NOF = 3) precede the next data. To set up this sequence correctly,
the PAD value must not exceed NOF.
Figure 5-4. Relation between PAD and NOF
6
CM
Continuous mode
0 Normal operation.
1 The R bit is not cleared by the CPM after this buffer descriptor is closed, allowing the
associated data buffer to be retransmitted automatically when the CPM next accesses this
buffer descriptor.
7—
—
8
UB
User bit—The CPM never touches, sets, or clears this user-dened bit. The user determines how
this bit is used. For example, it can be used to signal between higher-level protocols whether a
buffer has been processed by the CPU.
9–11
—
12–15
PAD
Padding bits—These four bits indicate the number of PAD characters (0x7E or 0xFF depending
on IDLM mode in the CHAMR register) that the transmitter sends after the closing ag. The
transmitter issues a TXB interrupt only after sending the programmed value of pads to the Tx
FIFO. The user can use the PAD value to guarantee that a TXB interrupt occurs after the closing
ag has been sent on the TXD line. PAD = 0 means the TXB interrupt is issued immediately after
sending the closing ag to the Tx FIFO.
The number of PAD characters depends on the FIFO size and the number of time slots in use. An
example explains the calculation: In SCC1 the FIFO is 32 bytes. If 16 time slots are used in the
link, the resulting number of PAD characters is 32/16 = 2, to append to this buffer to ensure that
the TXB interrupt is not given before the closing ag has been transmitted through the TXD line.
The number of PAD characters must not exceed the NOF characters, ensuring that the closing of
one buffer (the interrupt generation) occurs before the start of the next frame (clearing of R-bit).
After the sequence of a closing ag followed by (PAD + 1) ag characters, a TXB interrupt will be
generated; see Figure 5-4.
16–31
DL
Data length—The data length is the number of bytes the CPM should transmit from this buffer
descriptor’s data buffer. It is never modied by the CPM. This eld should be greater than zero.
32–63
TxBP
Tx buffer pointer—The transmit buffer pointer, which contains the address of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory. This
value is never modied by the CPM.
Table 5-2. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued)
Field
Name
Description
DATA
CRC
FLG
PAD=1, NOF=3
DATA
TXB INTERRUPT
CLEARING R-BIT
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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