參數(shù)資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 158/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 6. QMC Initialization
MFLR/MRBLR: MFLR (HDLC mode)—application-dependent.
MRBLR (transparent mode)—must be divisible by 4 and large (>30) for better
performance.
ch[x].MFLR = 60;
TRNSYNC: transparent synchronization, system-specic.
Step 17. Initialize RxBDs. Prepare an adequate number of receive buffers at the location
addressed by RBASE. In the status word, set the E bit, set the I bit if interrupts are required
and set the W bit for the last buffer descriptor. The data length is normally cleared, and the
buffer pointer is set to a location in external memory. See Section 5.1, “Receive Buffer
Descriptor,” for more information. Repeat for each enabled channel.
Step 18. Initialize TxBDs. Prepare an adequate number of transmit buffers at the location
addressed by TBASE. In the status word, set the R bit, set the I bit if interrupts are required,
and set the W bit for the last buffer descriptor. Other options are available and may be set
or cleared depending on the application. The data length is written with the number of bytes
to transmit, and the buffer pointer is set to a location in external memory. See Section 5.2,
“Transmit Buffer Descriptor,” for more information. Repeat for each enabled channel.
Step 19. Initialize the circular interrupt table. If interrupts are required, initialize the
interrupt table as explained in Chapter 4, “QMC Exceptions.” Clear the V and W bits, but
make sure to set the last entry’s W bit.
Step 20. Initialize the channel mode register CHAMR (see Table 6-6). For more
information see Section 2.4.1.1, “CHAMR—Channel Mode Register (HDLC),” for HDLC
mode and Section 2.4.2.1, “CHAMR—Channel Mode Register (Transparent Mode),” for
transparent mode.
Table 6-6. CHAMR Bit Settings
Name
Number of Bits
Description
Setting
MODE
1
0—transparent; 1—HDLC
X
RD/0
1
Transparent only: reverse data
X
1/IDLM
1
HDLC only: idle mode
X
ENT
1
Enable transmit
0
SYNC
1
Transparent only: synchronization
X
POL
1
Enable polling
0
CRC
1
HDLC only: CRC
X
NOF
4
Minimum number of ags
X
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
FMC43DRXH-S734 CONN EDGECARD 86POS DIP .100 SLD
FMC36DRYS-S93 CONN EDGECARD 72POS .100 DIP SLD
MC68MH360VR33L IC MPU QUICC 33MHZ 357-PBGA
FMM43DSES-S243 CONN EDGECARD 86POS .156 EYELET
FSM44DSEF-S243 CONN EDGECARD 88POS .156 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68MH360ZQ33LR2 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68P11E1CFN2R2 制造商:Rochester Electronics LLC 功能描述:8BIT MCU 512RAM A/D EE - Bulk
MC68P11E1CFNE2R 功能描述:8位微控制器 -MCU 8B MCU 512 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68P-3-2 制造商:PARKER 功能描述:
MC-68PLCC 制造商:SPC Multicomp 功能描述:SOCKET PLCC 68 PIN THRU-HOLE 制造商:SPC Multicomp 功能描述:SOCKET, PLCC, 68 PIN, THRU-HOLE 制造商:PRIVATE LABEL 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of C 制造商:SPC Multicomp 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of Contacts:68, Pitch Spacing:1.27mm, Contact Termination:Through Hole Vertical, Contact Material:Phosphor Bronze, Contact Plating:Tin , RoHS Compliant: Yes
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*