參數(shù)資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 109/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
2.4.2.3 INTMSK—Interrupt Mask (Transparent Mode)
Each event dened in the interrupt circular queue entry maps directly to a bit in INTMSK
as shown in Figure 2-13. There is one mask bit for each event—UN (bit 11), BSY (bit 13),
TXB (bit 14) and RXB (bit 15). Bits that do not map to an event are reserved. Reserved bits
must be set to zero.
0 = No interrupt request is generated and no new entry is written in the circular
interrupt table.
1 = Interrupts are enabled.
This register is initialized by the host before operation.
INTERRUPT TABLE ENTRY:
INTMSK:
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-13. INTMSK and Interrupt Table Entry (Transparent Mode)
2.4.2.4 TRNSYNC—Transparent Synchronization
In transparent mode, the TRNSYNC register controls the synchronization for single time
slots or superchannel applications.
Note
This register has no meaning if the SYNC bit in the channel
mode register (CHAMR) is cleared (0).
When sending a transparent message over several time slots, it is necessary to know in
which time slot the rst byte of data appears.
The TRNSYNC word-length register is divided into two parts with the high byte
controlling the rst received time slot and the low byte controlling the transmitter
synchronization.
0
123456789
10
11
12
13
14
15
V
W
RES
–
CHANNEL NUMBER
RES
UN
RES
BSY
TXB
RXB
RESET:
0
000000000000000
0
123456789
10
11
12
13
14
15
RESERVED
RES
INTERRUPT MASK BITS
Reset:
0
000000000000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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