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| 型號(hào)： | MC68MH360ZQ33L |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 48/158頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤(pán) |
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Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
However, this conguration works only if the single master S/T or U interface is guaranteed
to be active, constantly generating synchronized DCL and FSC signals for the network.
Since the designated master transceiver cannot be guaranteed active, all transceivers must
be congured in slave mode, and the problem of synchronization remains.
DCL and FSC must be generated from within the network and cannot be derived from an
independent source (e.g., crystal or oscillator). However, the S/T and U interfaces, even in
slave mode, provide a way to generate these signals as explained in the following sections.
C.3.1 MC145574 S/T Interface
To facilitate the generation of timing signals required by the slave IDL interface, TCLK is
provided in the S/T interface. The TCLK signal will output a clock synchronized to the
received data transmitted by the NT. That clock is output only when the S/T interface is
active and when the DCL and FSC signals are present (both conditions are required
simultaneously). This TCLK signal can be used to provide network timing. Its frequency is
selectable via the SCP.
The TCLK signal of the MC145574 is enabled by setting OR7[5]. BR13[5] and BR7[2]
determine the TCLK frequency as shown in Table C-1.
A TCLK signal congured as a 2.048-MHz clock can be used as the DCL for the IDL bus.
Dividing the TCLK signal by 256 provides the 8-KHz frame sync FSC. Since the FSC must
have a pulse between one DCL and eight DCLs in width, additional logic may be needed
after the divider to generate a signal with a correct duty cycle.
Figure C-4 and Figure C-5 show a schematic and a timing diagram, respectively, for a logic
design used to generate a 8-KHz FSC with a 1-DCL width pulse from a 2.048-MHz clock
(TCLK).
Table C-1. TCLK Frequencies Selected by BR13[5] and BR7[2]
BR13[5]
BR7[2]
TCLK
0
2.56 MHz
0
1
2.048 MHz
1
0
1.536 MHz
1
512 KHz
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