參數(shù)資料
型號(hào)： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 155/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
Clear the ENR and ENT bits at the end of the initialization. The MODE setting for QMC
mode is 0b1010.
A typical setting would be:
GSMR_L = 0x0000_000A;
/* enable QMC */
Step 11. Initialize basic global multichannel parameters as follows. See Chapter 2, “QMC
Memory Organization,” for more information.
MCBASE: (multichannel base pointer) is a pointer to a 64-Kbyte buffer descriptor
table in external memory. For example:
SCC1.MCBASE = 0x1_0000;
/* BD base located 0x1_0000 */
INTBASE: (interrupt table base pointer) - points to the interrupt table in external
memory. For example:
SCC1.INTBASE = 0xF000;
/* interrupt table base 0xF000 */
MRBLR: (maximum receive buffer length) - should be large (> 30) for better
performance and should be a multiple of 4 bytes. This is valid for HDLC only. For
example:
SCC1.MRBLR = 60;
/* set receive buffer length to 60 */
GRFTHR: (global receive frame threshold) - normally set to 1. For example:
SCC1.GRFTHR = 1;
/* 1 receive frame to interrupt */
GRFCNT: (global receive frame count) - should be initialized to the same value as
GRFTHR. For example:
SCC1.GRFCNT = 1;
/* 1 receive frame to interrupt */
C_MASK32:CRC constant, 32-bit =0xDEBB20E3
SCC1.C_MASK32 = 0xDEBB20E3;
/* init 32-bit CRC const */
C_MASK16:CRC constant,16-bit=0xFOB8
SCC1.C_MASK16 = 0xF0B8;
/* init 16-bit CRC const */
Step 12. Copy INTBASE to INTPTR (multichannel interrupt pointer). See Chapter 4,
“QMC Exceptions,” for more information.
SCC1.INTPTR = SCC1.INTBASE;
/* init intptr */
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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