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Interrupt and Exception Handling
5-12
MC68322 USER’S MANUAL
MOTOROLA
5.4.2.5 PRIVILEGE VIOLATIONS. To provide system security, various instructions are
privileged. An attempt to execute one of the privileged instructions while in the user mode
causes an exception. The privileged instructions are as follows:
and immediate to sr
move usp
eor immediate to sr
or immediate to sr
move to sr
reset
move from sr
rte
movec
stop
moves
Exception processing for privilege violations is nearly identical to that for illegal instructions.
The core starts exception processing once the instruction is fetched, decoded, and the core
determines that a privilege violation is being attempted. The internal status register is
copied, the supervisor mode is entered, and tracing is turned off. The vector number is
generated to reference the privilege violation vector and the current internal program
counter and copy of the internal status register are saved on the supervisor stack. The saved
value of the internal program counter is the address of the first word of the instruction
causing the privilege violation. Finally, instruction execution commences at the address in
the privilege violation exception vector.
5.4.2.6 TRACING. To aid in program development, the core includes a facility to allow
tracing after each instruction. When tracing is enabled, an exception is forced after the
execution of each instruction. Thus, a debugging program can monitor the execution of the
program under test.
The trace facility is controlled by the T bit in the supervisor portion of the internal status
register. If the T bit is cleared, tracing is disabled and instruction execution proceeds from
instruction to instruction as normal. If the T bit is set (on) at the beginning of an instruction’s
execution, a trace exception is generated after the completion of the instruction. If the
instruction is not executed because an interrupt is taken or because the instruction is illegal
or privileged, the trace exception does not occur. The trace exception also does not occur if
the instruction is aborted by a reset, bus error, or address error exception. If the instruction
is executed and an interrupt is pending on completion, the trace exception is processed
before the interrupt exception. During the execution of the instruction, if an exception is
forced by that instruction, the exception processing for the instruction exception occurs
before that of the trace exception.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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