![](http://datasheet.mmic.net.cn/30000/MC68322FT16_datasheet_2368702/MC68322FT16_6.png)
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
viii
MC68322 USER’S MANUAL
MOTOROLA
Section 3
The Core
3.1
Programming Model ............................................................................. 3-1
3.2
Data Types and Addressing Modes ..................................................... 3-3
3.3
Instruction Set Summary ...................................................................... 3-4
Section 4
Bus Operation
4.1
EC000 Core Read Cycle ...................................................................... 4-1
4.2
EC000 Core Write Cycle ...................................................................... 4-4
4.3
Interrupt Acknowledge Bus Cycle ........................................................ 4-6
4.4
Reset Operation ................................................................................... 4-8
4.5
External Bus Master ............................................................................. 4-9
4.5.1
MC68322 Bus Arbitration ........................................................... 4-9
4.5.2
External Bus Master Read Cycle ............................................. 4-10
4.5.3
External Bus Master Write Cycle ............................................. 4-11
4.5.4
Illegal Address Interrupt ........................................................... 4-12
Section 5
Interrupt and Exception Handling
5.1
Internal Interrupts ................................................................................. 5-1
5.1.1
Hardware Interrupts ................................................................... 5-2
5.1.2
Software Interrupts ..................................................................... 5-3
5.2
External Interrupts ................................................................................ 5-4
5.3
Timer Module ....................................................................................... 5-6
5.4
Core Exception Handling ..................................................................... 5-7
5.4.1
Processing Specific Exceptions ............................................... 5-10
5.4.2
Multiple Exceptions .................................................................. 5-13
5.4.3
Exception Bus Cycles .............................................................. 5-14
5.5
Module Soft-Reset Register ............................................................... 5-14
Section 6
System Integration Module
6.1
Chip-Select Registers And Banks ........................................................ 6-1
6.2
Synchronous and AsynchronouS Chip-Select Access Timing ............ 6-4
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.