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MOTOROLA
MC68322 USER’S MANUAL
10-1
SECTION 10
PRINT ENGINE INTERFACE
The MC68322 uses an 8-bit, half-duplex, synchronous serial protocol to communicate with
the print engine. This print engine interface contains an integrated print engine video
controller (PVC) as well as control logic for the 8-bit serial communication channel
compatible with many print engines. The print engine interface is one of the two components
of the graphics unit; the other being the RISC graphics processor.
The PVC can drive virtually all laser printers currently on the market. It automatically
retrieves video data from DRAM using burst cycles and manages all parameters associated
with the video image. This type of print engine video interface eliminates all the software
overhead associated with the transfer of the bitmap image to the print engine. The software
starts the transfer and waits for the end of page or band interrupt event, which allows the
core to start processing the next page. The PVC also saves a significant amount of
hardware cost. Static RAMs and FIFOs are unnecessary since the bitmap image is
transferred directly from DRAM, serialized, and then transmitted to the print engine. The
PVC uses an efficient page mode access to DRAM to fill its internal eight word queue
(FIFO).
The PVC is divided into two subsystems:
A memory subsystem that performs direct memory accesses to DRAM to obtain video
data from a page or band bitmap.
A video subsystem that serializes the data and handshakes with the printer to transmit
the video data.
The memory subsystem contains a data fetch controller, an 8-word deep FIFO, and many
counters. It interfaces to the core through a set of memory-mapped registers called the
printer control block. The video subsystem’s task is to interface with the print engine and
serialize and transmit video data. It contains a video interface controller, a 16-bit shift
register, a phase-locked loop (PLL) clock circuit, and some counters.
The PLL video clock divisor divides the VCLK input by 32, 24, 16, 12, 8, or 4 to produce the
dot clock for the PVC. This is accomplished internally by using a prescaler and by using
either the rising edge or both edges of the clock for the PLL. This feature allows for direct
support of multiple resolutions using a single external oscillator. For example, the PVC can
transmit 300
× 300, 600 × 300, 600 × 600, or 1200 × 600 resolution page images using the
same VCLK input frequency.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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