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| 型號： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 94/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
72
Table 18. SERDES Per-Quad Control Register Descriptions
(0x) Abso-
lute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Per-Quad Control Register (Read/Write) xx = [AA, ...,BD]
30005 - A
30105 - B
[0]
RSVD
44
Reserved
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the
transmit and receive alarms of all channel in
the SERDES quad are prevented from generat-
ing an alarm (i.e., they are masked or disabled).
The GMASK_[A:B] bit overrides the individual
MASK_xx bits. GMASK_[A:B] = 1 on device
reset.
Both
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit pro-
vides the same function as the hardware reset
for the transmit and receive sections of all four
channels, except that the device conguration
settings are not affected when GSWRST_[A:B]
is asserted. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared.
The GSWRST_[A:B] bit overrides the individual
SWRST_xx bits.
GSWRST_[A:B] = 0 on device reset.
Both
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When
GPWRDNT_[A:B] = 1, sections of the transmit
hardware for all four channels are powered
down. The GPWRDNT_[A:B] bit overrides the
individual PWRDNT_xx bits.
GPWRDNT_[A:B] = 0 on device reset.
Both
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When
GPWRDNR_[A:B] = 1, sections of the receive
hardware for all four channels are powered
down. The GPWRDNR_[A:B] bit overrides the
individual PWRDNR_xx bits.
GPWRDNR_[A:B] = 0 on device reset.
Both
[5]
GTRISTN_[A:B]
Active-low TRISTN function. When GTRISTN =
1, the CMOS output buffers for SERDES A are
tristated.
Both
[6:7]
RSVD
Reserved
30006 - A
30106 - B
TESTMODE_[A:B]
00
Test mode for SERDES characterization
Both
RSVD
Reserved
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