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參數(shù)資料
| 型號(hào)： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 66/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
47
Figure 32. Cell Mapping in SONET Frame
The cells are placed in a SONET frame such that the rst cell starts at the rst SPE column of the rst row (145th
column. 144 columns are taken up by TOH). Subsequent cells are placed contiguously, skipping the Transport
OverHead (TOH) columns when appropriate.
The ORSO82G5 supports four cell sizes with varying payloads. The total cell size sent across the backplane is the
combined size of the user cell payload (cell header and data), user BIP and the Link Header byte. Table 7 indicates
the cell sizes supported by the ORSO82G5 within a STS-48c frame. Only one cell size can be used at a time.
Table 7. ORSO82G5 Supported Cell Sizes
NOTE: To calculate the number of Cells per SPE:
[(87Rows/STS-1*9Columns/STS-1)octets/(STS-1 SPE)] * 48 STS-1 = 37584 octets
337584 / TOTAL CELL SIZE = # of cells per SPE.
A cell cannot span multiple SONET frames. This implies that there may be some cell sizes for which some bytes
will be unused at the end of a SPE. These are called pad bytes.
Each cell is preceded by a Link Header byte as shown in Figure 33. Table 8. denes the format of the Link Header.
The Link Header byte is useful for cell delineation when cell data are striped across multiple links. The link header
is inserted automatically in the transmit direction by the IPC block. The Link Header is checked in the receive direc-
tion and removed by the OPC before the cell is sent across the core/FPGA interface.
Total Cell Size
(across B/P)
User Cell Payload
Size
(header/data)
Link Header
Byte
User BIP
Field
Cells/Frame
Number of Pad
Bytes Per SPE
77
75
1
488
8
81
79
1
464
0
85
83
1
442
14
93
91
1
404
12
TO
H
BYTES
A1 A2 J0
Cell 0
Cell 1
Cell 2 (etc.)
Link Header byte
Pad bytes
CELL
P
A
YLO
AD
BYTES
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| M-ORSO82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G51BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
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