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| 型號(hào)： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 37/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
20
SERDES Transmit and Receive PLLs
The high-speed transmit and receive serial data can operate at 1.0—2.7 Gbits/s depending on the state of the con-
trol bits from the MicroProcessor Interface. Figure 2 shows the relationship between the data rates, the reference
clock, and the internal transmit TCK78x clocks.
Table 2. Transmit PLL Clock and Data Rates
Note:The selection of full-rate or half-rate for a given reference clock speed is set by the TXHR bit in the transmit
control register and can be set per channel. (For cell mode all channels of a group must have the same TXHR
selection.)
Note:In selections of this data sheet, the differential clocks are simply referred to as the reference clock
REFCLK_[A:B]. REFCLK_[A:B] is equivalent to REFINP_[A:B] and REFINN_[A:B].
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as a 8-bit parallel data on
the output port. RWCKx receive byte clocks are divide-by-4 clocks of the RBC0 or RBC1 (recovered clock) clocks
provided by the SERDES. This is the clock used in the internal receive functions of the embedded core.
The reference clock is also used by the receive PLL for operation when the input data are not toggling appropri-
ately. Table 3 shows the relationship between the data rates, the reference clock, and the RWCKx clocks.
Table 3. Receive PLL Clock and Data Rates
Note:The selection of full-rate or half-rate for a given reference clock speed is set by the RXHR bit in the receive
control register and can be set per channel. (For cell mode all channels of a group must have the same RXHR
selection.)
The differential reference clock is distributed to all four channels per quad SERDES block. Each channel has a dif-
ferential buffer to isolate the clock from the other channels. The input clock is preferably a differential signal; how-
ever, the device can operate with a single-ended input. The input reference clock directly impacts the transmit data
eye, so the clock should have low jitter. In particular, jitter components in the dc—5 MHz range should be mini-
mized.
Data Rate
Reference Clock
TCK78x
Rate
1.0 Gbits/s
125.00 MHz
31.25 MHz
Half
1.244 Gbits/s
155.52 MHz
38.88 MHz
Half
1.35 Gbits/s
168.75 MHz
42.19 MHz
Half
2.0 Gbits/s
125.00 MHz
61.50 MHz
Full
2.488 Gbits/s
155.52 MHz
77.76 MHz
Full
2.7 Gbits/s
168.75 MHz
84.38 MHz
Full
Data Rate
Reference Clock
RWCKx Clocks
Rate
1.0 Gbits/s
125.00 MHz
31.25 MHz
Half
1.244 Gbits/s
155.52 MHz
38.88 MHz
Half
1.35 Gbits/s
168.75 MHz
42.19 MHz
Half
2.0 Gbits/s
125.00 MHz
61.50 MHz
Full
2.488 Gbits/s
155.52 MHz
77.76 MHz
Full
2.7 Gbits/s
168.75 MHz
84.38 MHz
Full
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