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| 型號(hào)： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 68/123頁(yè) |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
49
number 37. The cell will be marked with an error. The receiver then expects to receive a cell with sequence number
28.
Cell Mode Transmit Path
In the transmit path in cell mode, the transmit logic creates a SONET-like transport frame for the data, adds the
required Transport OverHead bytes (cell mode automatically uses AUTO_TOH mode) and retimes the cell data
from the FPGA interface rate of 156 MHz to the framer rate of 77.76 MHz. The data are then sent to the SONET
logic blocks and SERDES. The Payload sub-block of the SONET logic operates somewhat differently than in
SONET mode, however.
Output Port Controller
In cell mode the Output Port Controller (OPC) is the block responsible for directing trafc for the egress cell trafc
ow. These are the blocks that provides the interface between FPGA and the Transmit FIFO. There is one eight-
link controller (OPC8) and four two-link controllers (OPC2s). The user provides the 160-bit (OPC8) or 40-bit
(OPC2) cell data, and a cell_vaild strobe to the OPC. No Link Header byte is sent with the cell data. The OPC pro-
vides the following functions:
Accepts cell payload from the FPGA logic and assembles legal output cells from these.
Schedules, manages and performs writes of cell data into TX FIFOs in the transmit framer blocks of all the eight-
links or up to 4 pairs of two-links.
Provides backpressure information to the FPGA to stop writes to the TXFIFO if the FIFO is not ready to accept
data.
The 5 OPC blocks operate as follows:
OPC8 to stripe cells across eight-links
OPC2_A1 to service links AA,AB
OPC2_A2 to service links AC,AD
OPC2_B1 to service links BA,BB
OPC2_B2 to service links BC,BD
When operating with some links in the two-link cell mode, links not in an alignment group can optionally be oper-
ated in a SONET mode.
The OPC2 blocks run at 39 MHz. The input from FPGA is a 40-bit bus at 156 MHz (4 times the required frequency).
A 1:4 deMUX block provides a 160-bit bus at 39 MHz
相關(guān)PDF資料 |
PDF描述 |
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| M-ORSO82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G51BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| M-ORT82G52BM680-DB | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
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