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| 型號： | M-ORSO82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 22/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G51BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
118
θJB
This is the thermal resistance from junction to board (ΘJL). It is dened by:
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters
on the right-hand side have been dened above. This is considered a true thermal resistance, and the measure-
ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads.
Note that θJB is expressed in units of °C/W and that this parameter and the way it is measured are still being dis-
cussed by the JEDEC committee.
FPSC Maximum Junction Temperature
Once the power dissipated by the FPSC has been determined (see the Estimating Power Dissipation section), the
maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the
device from the 85 °C junction temperature used in all of the delay tables is needed. Using the maximum ambient
temperature, TAmax, and the power dissipated by the device, Q (expressed in °C), the maximum junction tempera-
ture is approximated by:
TJmax = TAmax + (Q θJA)
Table 36 lists the thermal characteristics for all packages used with the ORCA ORSO82G5 Series of FPSCs.
Package Thermal Characteristics
Table 36. ORCA ORSO82G5 Plastic Package Thermal Guidelines
Note: The 680-pin PBGAM package for the ORSO82G5 includes a heat spreader.
Package Coplanarity
The coplanarity limits of the Lattice packages are as follows:
PBGAM: 8.0 mils
Package
θθ
θ
θJA (°C/W)
Maximum Power (W)
0 fpm
200 fpm
500 fpm
T = 70 °C Max,
TJ = 125 °C Max,
0 fpm
680-Pin PBGAM
9.8
7.8
6.8
4.1
ΘJB
TJ TB
–
Q
-------------------
=
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