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參數(shù)資料
| 型號(hào)： | LH7A404N0F000B3 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 32-Bit System-on-Chip |
| 封裝： | LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT |
| 文件頁數(shù)： | 44/75頁 |
| 文件大?。?/td> | 1109K |
| 代理商： | LH7A404N0F000B3 |
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LH7A404
32-Bit System-on-Chip
44
Preliminary data sheet
NXP Semiconductors
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter,
power rail noise, and I/O condtioning will cause these timings to vary nominally. It is recommended that
designers add a small margin to avoid possible corner-case conditions.
2. The Bank Configuration Register (BCRx:WST1) must have Write Wait States set to a minimum of 2.
3. The number of HCLK periods that nWAIT lags assertion of nCSx must be added to the minimum value
for BCRx:WST1. For example, if nWAIT lags nCSx by 3 HCLK periods, the minimum setting of BCRx:WST1
is 2 + 3, or a total of 5 as the minimum value for BCRx:WST1.
4. No nWAIT delay cycles are added for any nWAIT assertions that occur prior to the beginning of the WSD-2 delay. These
nWAIT assertions are ignored.
5. Once the WSD-2 delay begins, one HCLK cycle is added to the transaction each time nWAIT is
sampled and queued (SQ-x). The nWAIT cycles begin being added after the Wait State Countdown reaches WSD-0.
6. Once nWAIT is sampled HIGH (de-asserted), the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, prolonged extension of
an SMC transaction by either Wait States or nWAIT delays can cause refresh failure for the SDRAM,
and may cause SDRAM data loss.
Figure 15. nWAIT Write Sequence (BCRx:WST1 = 2); Minimum Wait State Example
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT
1
tIDA_nCS(x)_nWAIT
Delay from nCS(x) assertion to nWAIT assertion
0
29
HCLK periods
tDD_nWAIT_nCS(x)
Delay from nWAIT deassertion to nCS(x) deassertion
4
HCLK periods
tDD_nWAIT_nWE
Delay from nWAIT deassertion to nWE deassertion
3
HCLK periods
tA_nWAIT
Assertion time of nWAIT
2
HCLK periods
tDA_nCS(x)_nWAIT
HCLK
nCS(x)
nWE
nWAIT
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
tA_nWAIT
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
LH7A404-206
WSD-2
DELAY
WSD-1
DELAY
WSD-0
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
SQ-0
nWAIT
DELAY
END
CYCLE
Transaction
Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A404N0F000B3,55 | 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A404N0F000B3,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A404N0F000B3;55 | 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A404N0F000B3;55 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 200MHZ LFBGA-324 |
| LH7A404N0F000B3-S | 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
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