參數(shù)資料
型號(hào): LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 22/75頁
文件大?。?/td> 1109K
代理商: LH7A404N0F000B3
LH7A404
32-Bit System-on-Chip
22
Preliminary data sheet
NXP Semiconductors
Vectored Interrupt Controller (VIC)
The LH7A404 has two VICs working together to
manage interrupt requests from on-chip and off-chip
sources. Each VIC performs these primary functions:
Determine if an interrupt source is disabled or can
generate an FIQ or IRQ to the ARM core
Prioritize up to 16 separate interrupt sources for
simultaneous and nested processing
Obtain the address of the interrupt handler (vector)
for up to 16 interrupt sources
Provide a default vector and a set of status registers
for up to 16 non-vectored sources. Software deter-
mines the priority of these interrupts.
Two VICs are daisy-chained together to support up
to 64 different interrupts, 32 of which are vectored. The
VIC supports both FIQ and IRQ interrupts. FIQ inter-
rupts have a higher priority than IRQ interrupts. If two
interrupts with the same priority become active at the
same time, the priority must be resolved in software.
When an interrupt becomes active, the VIC generates
an FIQ or IRQ if the corresponding mask bit is set.
Interrupts are not latched in the VIC, but may latch on
a particular peripheral when applicable.
After a power-on reset, all mask register bits are
cleared, masking all interrupts. They must be set by
software after power-on reset to enable interrupts.
A vectored interrupt has improved latency as it pro-
vides direct information about where its service routine
is located and eliminates software arbitration needed
with a simple interrupt controller.
The VICs continue to operate in Halt and Standby
modes, so external interrupts may bring the chip out of
these low power modes.
External Bus Interface
The ARM922T, LCD controller, and DMA engine
have access to an external memory system. The LCD
controller has access to an internal frame buffer in
embedded SRAM and an extension buffer in Synchro-
nous Memory for large displays. The processor and
DMA engine share the main system bus, providing
access to all external memory devices and the embed-
ded SRAM frame buffer.
An arbitration unit ensures that control over the
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 4.
Figure 4. External Bus Interface Block Diagram
ARM922T
LCD
CONTROLLER
EMBEDDED
SRAM
80KB
LCD AHB BUS
SYSTEM AHB BUS
LCD
MMU/DMA
DMA
CONTROLLER
USB
HOST
ASYNCHRONOUS
MEMORY
CONTROLLER
(SMC)
SYNCHRONOUS
MEMORY
CONTROLLER
(SDMC)
EXTERNAL
BUS
INTERFACE
(EBI)
A
SDRAM
SRAM
SDRAM
ROM
DATA
ADDRESS/
CONTROL
LH7A404-8
INTERNAL TO
THE LH7A404
EXTERNAL TO
THE LH7A404
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