參數(shù)資料
型號(hào): LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 23/75頁
文件大?。?/td> 1109K
代理商: LH7A404N0F000B3
32-Bit System-on-Chip
LH7A404
Preliminary data sheet
23
NXP Semiconductors
Embedded SRAM
The LH7A404 incorporates 80 kB of embedded
SRAM. This embedded memory is used for storing
code, data, or LCD frame data and is contiguous with
external SDRAM. The 80 kB is large enough to store a
QVGA frame (320 × 240) at 8 bits per pixel, equivalent
to 70 kB of information.
Locating the frame buffer on chip reduces the overall
power consumed by LH7A404 applications. Normally,
the system performs external accesses to acquire this
data. The LCD controller automatically uses an over-
flow frame buffer in SDRAM if a larger screen size is
required. This overflow buffer can be located on any
4 kB page boundary in SDRAM, allowing software to
set the MMU (in the LCD controller) page tables so the
two memory areas appear contiguous, allowing byte,
half-word, and word accesses.
Static Memory Controller (SMC)
The asynchronous Static Memory Controller (SMC)
provides an interface between the AMBA AHB system
bus and external (off-chip) memory devices.
The SMC simultaneously supports up to eight inde-
pendently configurable memory banks. Each memory
bank can support:
SRAM
ROM
Flash EPROM
Burst ROM memory.
Each memory bank may use devices with either
8-, 16-, or 32-bit external memory data paths. The
memory controller is configured to support little-endian
operation only.
The memory banks can be configured to support:
Non-burst read and write accesses only to high-
speed CMOS static RAM
Non-burst write accesses, nonburst read accesses
and asynchronous page mode read accesses to
fast-boot block flash memory.
The SMC has six main functions:
Memory bank select
Access sequencing
Wait state generation
Byte lane write control
External bus interface
CompactFlash or PCMCIA interfacing.
SDRAM (Synchronous) Memory Controller
The SDRAM (Synchronous) Memory Controller pro-
vides a high speed memory interface to a wide variety of
synchronous memory devices, including Synchronous
DRAM, Synchronous Flash and Synchronous ROMs.
The key features of the controller are:
LCD DMA port for high bandwidth
Up to four Synchronous Memory banks can be inde-
pendently set up
Includes special configuration bits for Synchronous
ROM operation
Includes ability to program Synchronous Flash
devices using write and erase commands
On booting from Synchronous ROM, (and optionally
with Synchronous Flash), a configuration sequence is
performed before releasing the processor from reset
Data is transferred between the controller and the
Synchronous DRAM in four-word bursts. Longer
transfers within the same page are concatenated,
forming a seamless burst
Programmable for 16- or 32-bit data bus size
Two reset domains enable Synchronous DRAM con-
tents to be preserved over a ‘soft’ reset
Power saving Synchronous Memory SCKE and
external clock modes provided.
Secure Digital/MultiMediaCard (MMC)
The SD Memory Card is a flash-based memory card
that meets the security, capacity, performance,
and environment requirements inherent in electronic
devices. The SD Memory Card host supports
MultiMediaCard (MMC) operation as well, and is com-
patible with MMC Cards.
The SD/MMC controller can be used as an MMC
card controller or as an SD Card controller, and sup-
ports the full SD/MMC bus protocol as defined in the
MMC system specification 2.11 provided by the MMC
Association and the ‘SD Memory Card Spec v1.0’ from
the SD Association.
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