參數(shù)資料
型號(hào)： LH7A404N0F000B3
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： 32-Bit System-on-Chip
封裝： LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁(yè)數(shù)： 25/75頁(yè)
文件大?。?/td> 1109K
代理商： LH7A404N0F000B3
32-Bit System-on-Chip
LH7A404
Preliminary data sheet
25
NXP Semiconductors
The DMA Controller features:
Two dedicated channels for M2M and external
M2P/P2M
Ten fully independent, programmable DMA control-
ler internal M2P/P2M channels (5 Tx and 5 Rx)
Channels assignable to one of a number of different
peripherals
Independent source and destination address regis-
ters. Source and destination can be programmed
to auto-increment or not auto-increment for M2M
channels
Two buffer descriptors per M2P and M2M channel to
avoid potential data under/over-flow due to software
introduced latency. A buffer refers to the area in sys-
tem memory that is characterized by a buffer
descriptor, i.e., a start address and the length of the
buffer in bytes
No AMBA wrapping bursts for DMA channels; only
incrementing bursts are supported
Buffer size independent of the peripheral’s packet
size for the internal M2P channels. Transfers can
automatically switch between buffers
Maskable interrupt generation
Internal arbitration between DMA channels, plus
support for an AHB bus arbiter
DMA data transfer sizes, byte, word and quad-word
data transfers are supported using a 16-byte data.
Maximum data transfer size per M2M channel is
programmable
Per-channel clock gating reducing power in chan-
nels that have not been enabled by software. See
the ‘Clock and State Controller’ section.
A set of control and status registers are available to
the system processor for setting up DMA operations
and monitoring their status. System interrupts are gen-
erated when any/all of the DMA channels wish to
inform the processor to update the buffer descriptor.
The DMA controller can service 10 out of 20 possible
peripherals using the ten DMA channels, each with its
own peripheral DMA bus capable of simultaneously
transferring data in both directions.
The SD/MMC, UART[3:1], USB Device, and USB
Host peripherals can each use two DMA channels, one
for transmit and one for receive. The AC97 peripheral
can use six DMA channels (three transmit and three
receive) to allow different sample frequency data
queues to be handled with low software overhead.
The DMA controller includes an M2M transfer fea-
ture allowing block moves of data from one memory
address space to another with minimum of program
effort and time. An M2M software trigger capability is
provided. The DMA controller can also fill a block of
memory with data from a single location.
The DMA controller’s M2M channels can also be
used in M2P/P2M mode. A set of external handshake
signals, DREQ, DACK and TC/DEOT are provided for
each of two M2M channels.
DREQ (input) can be programmed edge or level
active, and active HIGH or LOW. The peripheral may
hold DREQ active for the duration of the block transfers
or may assert/deassert on each transfer.
DACK (output) can be programmed active HIGH or
LOW. DACK will assert and return to de-asserted with
each Read or Write, the timing coinciding with nOE or
nWE from the EBI.
TC/DEOT is a bidirectional signal with programma-
ble direction and active polarity. When configured as an
Output, the DMA will assert Terminal Count (TC) on the
final transfer to coincide with the DACK, typically when
the byte count has expired. When configured as an
Input, the peripheral must assert DEOT concurrent with
DREQ for the final transfer in the block.
Transfer is terminated when DEOT is asserted by the
external peripheral or when the byte count expires,
whichever occurs first. Status bits indicate if the actual
byte count is equal to the programmed limit, and if the
count was terminated by peripheral asserting DEOT.
Terminating the transfer causes a DMA interrupt on that
channel and rollover to the ‘other’ buffer if so configured.
USB Device
The features of the USB are:
Compliant with USB 2.0 Full Speed specification
Provides a high-level interface that removes the
USB protocol details from firmware
Compatible with both OpenHCI and Intel UHCI
standards
Supports full-speed (12 Mbit/s) functions
Supports Suspend and Resume signalling.
USB Host Controller
The features of the USB Host Controller are:
Open Host Controller Interface Specification (Open-
HCI) Rev. 1.0 Compliant
Universal Serial Bus Specification 2.0 Full Speed
compatible
Supports Low Speed and High Speed USB devices
Root Hub has two Downstream Ports
DMA functionality.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LH7A404N0F000B3,55 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LH7A404N0F000B3,551 制造商:NXP Semiconductors 功能描述:
LH7A404N0F000B3;55 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LH7A404N0F000B3;55 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 200MHZ LFBGA-324
LH7A404N0F000B3-S 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
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