參數(shù)資料
型號: LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 24/75頁
文件大?。?/td> 1109K
代理商: LH7A404N0F000B3
LH7A404
32-Bit System-on-Chip
24
Preliminary data sheet
NXP Semiconductors
SD/MMC INTERFACE DESCRIPTION
The SD/MMC controller uses the three-wire signal
bus (clock, command, and data) to input and output
data to and from the MMC, and to configure and
acquire status information from the card. The SD con-
troller differs in that it has four data lines instead of one.
The SD/MMC bus lines can be divided into three
groups:
Power supply: VSS1, VSS2, and VDD
Data transfer group: MMCCMD, MMCDATA0,
MMCDATA1, MMCDATA2, MMCDATA3 (for MMC,
do not use MMCDATA1, MMCDATA2, MMCDATA3)
Clock: MMCCLK
MMC CONTROLLER
The MMC controller implements MMC-specific func-
tions, serves as the bus master for the MMC Bus and
implements the standard interface to the MMC (card
initialization, CRC generation and validation, com-
mand/response transactions, etc.).
Smart Card Interface (SCI)
The SCI (ISO7816) connects to an external Smart
Card reader. The SCI can autonomously control data
transfer to and from the Smart Card. Transmit and
receive data FIFOs are provided to reduce the required
interaction between the CPU core and the peripheral.
SCI FEATURES
Supports asynchronous T0 and T1 transmission
protocols
Supports clock rate conversion factor F = 372, with
bit rate adjustment factors of D = 1, 2, or 4
Eight-character-deep buffered Tx and Rx paths
Direct interrupts for Tx and Rx FIFO level monitoring
Interrupt status register
Hardware-initiated card deactivation sequence on
detection of card removal
Software-initiated card deactivation sequence on
transaction complete
Limited support for synchronous smart cards via reg-
istered input/output.
PROGRAMMABLE PARAMETERS
Smart Card clock frequency
Communication baud rate
Protocol convention
Card activation/deactivation time
Maximum time for first character of Answer to Reset
(ATR) reception checking
Maximum ATR character stream duration checking
Maximum time of receipt of first character of data
stream checking
Maximum time allowed between characters checking
Character guard time
Block guard time
Transmit/receive character retry.
Direct Memory Access Controller (DMA)
The DMA Controller can be used to interface
streams from 20 internal peripherals to the system
memory using 10 fully-independent programmable
channels which consist of five M2P (transmit) channels
and five P2M (receive) channels.
The following peripherals may be allocated to the 10
channels:
USB Device
USB Host
SD/MMC
AC97
UART1
UART2
UART3
Each of the above peripherals contain one Tx and
one Rx channel, except the AC97, which contains three
Tx and Rx channels. These peripherals also have their
own bi-directional DMA bus, capable of simultaneously
transferring data in both directions. All memory trans-
fers take place via the main system AHB bus.
The DMA Controller can also be used to interface
streams from memory-to-memory (M2M) or memory-
to-external peripheral (M2P) using two dedicated
M2M channels. External handshake signals are avail-
able to support memory-to-/from-external peripheral
(M2P/P2M) transfers. A software trigger is available for
M2M transfers only.
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