參數(shù)資料
型號(hào)： ISPCLOCK5600
廠商： Lattice Semiconductor Corporation
英文描述： In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述： 在系統(tǒng)可編程，零延遲時(shí)鐘發(fā)生器通用扇出緩沖器
文件頁(yè)數(shù)： 36/47頁(yè)
文件大小： 871K
代理商： ISPCLOCK5600
Lattice Semiconductor
ispClock5600 Family Data Sheet
36
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being speci
fi
cally called out (all ones and all zeroes respec-
tively). The ispClock5000 contains the required minimum instruction set as well as one from the optional instruction
set. In addition, there are several proprietary instructions that allow the device to be con
fi
gured and veri
fi
ed. For
ispClock5000, the instruction word length is eight bits. All ispClock5000 instructions available to users are shown in
Table 8.
The following table lists the instructions supported by the ispClock5600 JTAG Test Access Port (TAP) controller:
Table 8. ispClock5600 TAP Instruction Table
BYPASS
is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the
ispClock5600. The IEEE 1149.1 standard de
fi
nes the bit code of this instruction to be all ones (111111).
The required
SAMPLE/PRELOAD
instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The bit code for this instruction is de
fi
ned by Lattice as shown in Table 8.
The
EXTEST
(external test) instruction is required and will place the device into an external boundary test mode
while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc-
tion is de
fi
ned by the 1149.1 standard to be all zeros (000000).
The optional
IDCODE
(identi
fi
cation code) instruction is incorporated in the ispClock5600 and leaves it in its func-
tional mode when executed. It selects the Device Identi
fi
cation Register to be connected between TDI and TDO.
The Identi
fi
cation Register is a 32-bit shift register containing information regarding the IC manufacturer, device
type and version code (Figure 32). Access to the Identi
fi
cation Register is immediately available, via a TAP data
Instruction
Code
Description
EXTEST
0000 0000
External Test.
ADDRESS_SHIFT
0000 0001
Address register (10 bits)
DATA_SHIFT
0000 0010
Address column data register (89 bits)
BULK_ERASE
0000 0011
Bulk Erase
Program column data register to E
2
PROGRAM
0000 0111
PROGRAM_SECURITY
0000 1001
Program Electronic Security Fuse
VERIFY
0000 1010
Verify column
DISCHARGE
0001 0100
Fast VPP Discharge
PROGRAM_ENABLE
0001 0101
Enable Program Mode
IDCODE
0001 0110
Address Manufacturer ID code register (32 bits)
Read UES data from E
2
and addresses UES register (32 bits)
Program UES register into E
2
USERCODE
0001 0111
PROGRAM_USERCODE
0001 1010
PROGRAM_DISABLE
0001 1110
Disable Program Mode
HIGHZ
0001 1000
Force all outputs to High-Z state
SAMPLE/PRELOAD
0001 1100
Capture current state of pins to boundary scan register
CLAMP
0010 0000
Drive I/Os with boundary scan register
USER_LOGIC_RESET
0010 0010
Resets User Logic
INTEST
0010 1100
Performs in-circuit functional testing of device.
ERASE DONE
0010 0100
Erases the ‘Done’ bit only
Program column data register to E
2
and auto-increment address register
Load column data register from E
2
and auto-increment address register
PROG_INCR
0010 0111
VERIFY_INCR
0010 1010
PROGRAM_DONE
0010 1111
Programs the ‘Done’ Bit
NOOP
0011 0000
Functions Similarly to CLAMP instruction
BYPASS
1xxx xxxx
Bypass - Connect TDO to TDI
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