參數(shù)資料
型號： ISPCLOCK5600
廠商： Lattice Semiconductor Corporation
英文描述： In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述： 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器
文件頁數(shù)： 16/47頁
文件大?。?/td> 871K
代理商： ISPCLOCK5600
Lattice Semiconductor
ispClock5600 Family Data Sheet
16
Table 2. PAC-Designer Recommended Loop Filter Settings
Note that the choice of loop
fi
lter parameters can have signi
fi
cant effects on settling time, output jitter, and whether
the PLL will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2
were chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that
when the skew mode is set to ‘coarse’, the effective value of NxV must be considered to have doubled. Refer to the
section titled ‘Coarse Skew Mode’ on page 28 for further details.
The PLLs loop bandwidth is a function of both the divider con
fi
guration and the loop
fi
lter settings. Figure 12 shows
the loop bandwidth as a function of the total feedback division ratio (N x V
FBK
). For each NxV feedback divider point
in this plot, the PLL loop
fi
lter was set to the corresponding value recommended in Table 2. The use of non-recom-
mended loop
fi
lter settings may result in signi
fi
cantly different bandwidths for a given NxV divider setting.
Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (nominal)
VCO
The ispClock5600 provides an internal VCO which provides an output frequency ranging from 320MHz to 640MHz.
The VCO is implemented using differential circuit design techniques which minimize the in
fl
uence of power supply
noise on measured output jitter. The VCO is also used to generate skews as a function of the total VCO period.
Using the VCO as the basis for controlling output skew allows for highly precise and consistent skew generation,
both from device-to-device, as well as channel-to-channel within the same device.
N x V
FBK
2 to 8
I (μA)
R (k
)
2.3
5
10
7
2.3
12 to 14
9
2.3
16
11
2.3
18 to 20
13
2.3
22
15
2.3
24 to 26
17
2.3
28
19
2.3
30
21
2.3
32 to 64
22
2.3
PLL Loop Bandwidth vs.
Feedback Divider Setting* (Typical)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0
16
32
48
64
N x V Feedback Division Product
*loop filter configured to recommended setting
L
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5620V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T100I In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T48C Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T48C LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm
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