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參數(shù)資料
| 型號： | ISPCLOCK5600 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPCLOCK5600 |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
12
Timing Speci
fi
cations (Cont.)
Boundary Scan Logic
JTAG Interface and Programming Mode
Symbol
Parameter
Min.
Max.
Units
t
BTCP
t
BTCH
t
BTCL
t
BTSU
t
BTH
t
BRF
t
BTCO
t
BTOZ
t
BTVO
t
BVTCPSU
t
BTCPH
t
BTUCO
t
BTUOZ
t
BTUOV
TCK (BSCAN Test) Clock Cycle
40
—
ns
TCK (BSCAN Test) Pulse Width High
20
—
ns
TCK (BSCAN Test) Pulse Width Low
20
—
ns
TCK (BSCAN Test) Setup Time
8
—
ns
TCK (BSCAN Test) Hold Time
10
—
ns
TCK (BSCAN Test) Rise and Fall Rate
50
—
mV/ns
TAP Controller Falling Edge of Clock to Valid Output
—
10
ns
TAP Controller Falling Edge of Clock to Data Output Disable
—
10
ns
TAP Controller Falling Edge of Clock to Data Output Enable
—
10
ns
BSCAN Test Capture Register Setup Time
8
—
ns
BSCAN Test Capture Register Hold Time
10
—
ns
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
—
25
ns
BSCAN Test Update Register, Falling Edge of Clock to Output Disable
—
25
ns
BSCAN Test Update Register, Falling Edge of Clock to Output Enable
—
25
ns
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
f
MAX
t
CKH
t
CKL
t
ISPEN
t
ISPDIS
t
HVDIS
t
HVDIS
t
CEN
t
CDIS
t
SU1
t
H
t
CO
t
PWV
t
PWP
t
BEW
Maximum TCK Clock Frequency
—
—
25
MHz
TCK Clock Pulse Width, High
20
—
—
ns
TCK Clock Pulse Width, Low
20
—
—
ns
Program Enable Delay Time
15
—
—
μs
Program Disable Delay Time
30
—
—
μs
High Voltage Discharge Time, Program
30
—
—
μs
High Voltage Discharge Time, Erase
200
—
—
μs
Falling Edge of TCK to TDO Active
—
—
15
ns
Falling Edge of TCK to TDO Disable
—
—
15
ns
Setup Time
8
—
—
ns
Hold Time
10
—
—
ns
Falling Edge of TCK to Valid Output
—
—
15
ns
Verify Pulse Width
30
—
—
μs
Programming Pulse Width
10
—
—
ms
Bulk Erase Pulse Width
200
—
—
ms
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPCLOCK5600A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5610A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5620A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPD60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| ISPD60_10 | 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT |
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