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參數(shù)資料
| 型號： | ISPCLOCK5600 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 27/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPCLOCK5600 |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
27
sumption by turning off unused drivers, these features can also be used for functional testing purposes. The follow-
ing inputs pins are used for output enable functions:
GOE – global output enable
OEX, OEY – secondary output enable controls
SGATE
– synchronous output control
Additionally, internal E
2
CMOS con
fi
guration bits are provided for the purpose of modifying the effects of these
external control pins.
When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal con
fi
guration. When
GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled
by the OEX and OEY pins. Internal E
2
CMOS con
fi
guration is used to establish whether the output driver is always
enabled (when GOE pin is LOW), never enabled (permanently off), or selectively enabled by the state of either
OEX or OEY. Bringing GOE high will also disable the internal feedback driver and will result in a loss of lock.
Synchronous output gating is provided by ispClock5600 devices through the use of the
SGATE
pin. The
SGATE
pin
does not disable the output driver, but merely forces the output to either a high or low state, depending on the out-
put driver’s polarity setting. If the output driver polarity is true, the output will be forced LOW when
SGATE
is
brought LOW, while if it is inverted, the output will be forced HIGH. A primary feature of the
SGATE
function is that
the clock output is enabled and disabled synchronous to the selected internal clock source. This prevents the gen-
eration of partial, ‘runt’, output clock pulses, which would otherwise occur with simple combinatorial gating
schemes. The
SGATE
is available to all clock outputs and is selectable on a bank-by-bank basis.
Table 5 shows the behavior of the outputs for various combinations of the output enables,
SGATE
input, and
E
2
CMOS con
fi
guration.
Table 5. Clock Output Enable Functions
Table 6. SGATE Function
Skew Control Units
Each of the ispClock5600’s clock outputs is supported by a skew control unit which allows the user to insert an indi-
vidually programmable delay into each output signal. This feature is useful when it is necessary to de-skew clock
signals to compensate for physical length variations among different PCB clock paths.
GOE
OEX
OEY
E
2
Con
fi
guration
Output
X
X
X
Always OFF
High-Z
0
X
X
Always ON
Clock Out
0
0
X
Enable on OEX
Clock Out
0
1
X
Enable on OEX
High-Z
0
X
0
Enable on OEY
Clock Out
0
X
1
Enable on OEY
High-Z
1
X
X
n/a
High-Z
SGATE Bank Controlled by SGATE
Output Polarity
Output
X
NO
True
Clock
X
NO
Inverted
Inverted Clock
0
YES
True
LOW
0
YES
Inverted
HIGH
1
YES
True
Clock
1
YES
Inverted
Inverted Clock
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ISPCLOCK5600A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
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| ISPCLOCK5620A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPD60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| ISPD60_10 | 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT |
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