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參數(shù)資料
| 型號： | ISPCLOCK5600 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 19/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPCLOCK5600 |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
19
Table 4. REFSEL and FBKSEL Operation for ispClock5620
LVTTL (3.3V)
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
Differential SSTL2
Differential SSTL3
Differential HSTL
LVDS
LVPECL (differential, 3.3V)
Each input also features internal programmable termination resistors, as shown in Figure 13. Note that all refer-
ence inputs (REFA+, REFA-, REFB+, REFB-) terminate to the REFVTT pin, while all feedback inputs (FBKA+,
FBKA-, FBKB+, FBKB-) terminate to the FBKVTT pin.
Figure 13. ispClock5600 Clock Reference and Feedback Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left
fl
oating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 14 shows the proper
con
fi
guration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate con
fi
guration setting for this particular standard.
REFSEL
Selected
Input Pair
FBKSEL
Selected
Input Pair
0
REFA+/-
0
FBKA+/-
1
REFB+/-
1
FBKB+/-
R
T
R
T
REFA-
REFA+
REFVTT
To Internal
Logic
Single-ended
Receiver
ispClock5600
Differential
Receiver
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| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPCLOCK5600A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5610A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5620A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPD60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| ISPD60_10 | 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT |
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