參數(shù)資料
型號： ISPCLOCK5600
廠商： Lattice Semiconductor Corporation
英文描述： In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述： 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器
文件頁數(shù)： 18/47頁
文件大?。?/td> 871K
代理商： ISPCLOCK5600
Lattice Semiconductor
ispClock5600 Family Data Sheet
18
Table 3. Nominal Output Duty Cycle vs. V-Divider Setting
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M divider
is routed directly to the inputs of the V dividers. In PLL_BYPASS mode, the nominal values of the V dividers are
halved, so that they provide division ratios ranging from 1 to 32. The output frequency for a given V divider (f
k
) will
be determined by
(2)
Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is
enabled, features such as lock detect and skew generation are unavailable.
Reference and External Feedback Inputs
The ispClock5600 provide sets of con
fi
gurable, internally-terminated inputs for both clock reference and feedback
signals. In normal operation, the one of the clock reference input pairs (REFA+/- or REFB+/-) is used as a clock
input.
The external feedback inputs make it possible to sample an output signal at the point of delivery. This makes it pos-
sible to provide output clocks which have very low skews in relation to the reference clock regardless of loading
effects.
The ispClock5610 provides one input signal pair for reference input and one input pair for external feedback, while
the ispClock5620 provides two pairs for reference signals and two pairs for feedback. To select between reference
and feedback inputs, the ispClock5620 provides two CMOS-compatible digital inputs called REFSEL and FBKSEL.
Table 4 shows the behavior of these two control inputs.
Divider Settings
with 50% Output
Duty Cycle
Divider Settings with
Non-50% Output Duty
Cycles
V
DC%
V
DC%
2
50
6
33
4
10
40
8
14
43
12
18
44
16
22
45
20
26
46
24
30
47
28
34
47
32
38
47
36
42
48
40
46
48
44
50
48
48
54
48
52
58
48
56
62
48
60
64
=
f
k
f
ref
x 2
M x V
k
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5620V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T100I In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T48C Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T48C LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPCLOCK5600A 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5610A 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5620A 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPD60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER
ISPD60_10 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT
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