- 您現在的位置：買賣IC網 > PDF目錄384544 > ISPCLOCK5600 (Lattice Semiconductor Corporation) In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer PDF資料下載
參數資料
| 型號： | ISPCLOCK5600 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數： | 2/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPCLOCK5600 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
Lattice Semiconductor
ispClock5600 Family Data Sheet
2
General Description and Overview
The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed
for use in high performance communications and computing applications. The ispClock5610 provides up to 10 sin-
gle-ended or
fi
ve differential clock outputs, while the ispClock5620 provides up to 20 single-ended or 10 differential
clock outputs. Each pair of outputs may be independently con
fi
gured to support separate I/O standards (LVDS,
LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro-
grammable control of termination, slew-rate, and timing skew. All con
fi
guration information is stored on-chip in non-
volatile E
CMOS memory.
2
The ispClock5600’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the
reference input through the provision of programmable input and feedback dividers. A set of
fi
ve post-PLL V-divid-
ers provides additional
fl
exibility by supporting the generation of
fi
ve separate output frequencies. Loop feedback
may be taken internally from the output of any of the
fi
ve V-dividers, or externally through FBKA+/- or FBKB+/- pins.
The core functions of all members of the ispClock5600 family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5610 and ispClock5620.
Table 1. ispClock5600 Family Members
Figure 1. ispClock5610 Functional Block Diagram
Device
Ref. Input Pairs
Feedback Input Pairs
Clock Outputs
ispClock5610
1
1
10
ispClock5620
2
2
20
VCO
LOOP
FILTER
PHASE
DETECT
LOCK
DETECT
M
N
INPUT
DIVIDER
FEEDBACK
SKEW ADJUST
1
0
FEEDBACK
DIVIDER
GOE
OEX
LOCK
PLL_BYPASS
JTAG INTERFACE
OEY
TDI
TMS
TCK
TDO
SGATE
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_5A
BANK_5B
BANK_7A
BANK_7B
OUTPUT
DIVIDERS
OUTPUT ROUTING
MATRIX
RESET
V1
V0
V3
V4
BANK_0A
BANK_0B
BANK_2A
BANK_2B
BANK_4A
BANK_4B
PS0
PS1
Profile Select
Control
0
1
2
3
OUTPUT ENABLE CONTROLS
(1-32)
(1-32)
(2-64)
(2-64)
(2-64)
(2-64)
(2-64)
REFA+
REFA-
REFVTT
FBKA+
FBKA -
FBKVTT
E
2
Configuration
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPCLOCK5600A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5610A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5620A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPD60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| ISPD60_10 | 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT |
發(fā)布緊急采購，3分鐘左右您將得到回復。