參數(shù)資料
型號(hào): ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 80/102頁(yè)
文件大小: 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
80 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.4.5
CTRLDSSEGMENT register (address: value read from func2 of address
10H + 1CH)
The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to
the most significant address bits (bits 63 to 32) for all EHCI data structures. If the
64AC (64-bit Addressing Capability) field in HCCPARAMS is cleared, then this
register is not used and software cannot write to it (reading from this register returns
zero).
If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is set, this register is
used with the link pointers to construct 64-bit addresses to EHCI control data
structures. This register is concatenated with the link pointer from either the
PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to
construct a 64-bit address.
This register allows the host software to locate all control data structures within the
same 4 Gigabyte memory segment.
11.4.6
PERIODICLISTBASE register (address: value read from func2 of address
10H + 20H)
The Periodic Frame List Base Address (PERIODLISTBASE) register contains the
beginning address of the Periodic Frame List in the system memory. If the Host
Controller is in the 64-bit mode (as indicated by a one in the 64AC (64-bit Addressing
Capability) field in the HCCSPARAMS register), then the most significant 32 bits of
every control data structure address comes from the CTRLDSSEGMENT register.
System software loads this register prior to starting the schedule execution by the
Host Controller. The memory structure referenced by this physical memory pointer is
assumed to be 4 kbyte aligned. The contents of this register are combined with the
FRINDEX register to enable the Host Controller to step through the Periodic Frame
List in sequence. The bit allocation is given in
Table 110
.
Table 110: PERIODICLISTBASE register: bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
Reset
0
Access
-
30
29
28
27
26
25
24
BA[19:12]
0
0
0
0
0
0
0
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
BA[11:4]
0
0
0
0
0
0
0
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
BA[3:0]
reserved
0
0
0
0
-
3
0
-
2
0
-
1
0
-
0
R/W
6
R/W
5
R/W
4
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
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