參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 59/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
59 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.1.21
HcRhStatus register (address: value read from func0 or func1 of address
10H
+
50H)
The HcRhStatus register is divided into two parts. The lower word of a DWord
represents the Hub Status field and the upper word represents the Hub Status
Change field. Reserved bits should always be written as logic 0.
Table 82
contains
the bit allocation of the register.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
DR[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 81:
Bit
31 to 16
HcRhDescriptorB register: bit description
Symbol
Description
PPCM[15:0]
PortPowerControlMask:
Each bit indicates whether a port is
affected by a global power control command when
PowerSwitchingMode is set. When set, the power state of the
port is only affected by per-port power control
(Set/ClearPortPower). When cleared, the port is controlled by
the global power switch (Set/ClearGlobalPower). If the device is
configured to global switching mode (PowerSwitchingMode = 0),
this field is not valid.
Bit 0 —
reserved
Bit 1 —
Ganged-power mask on Port #1
Bit 2 —
Ganged-power mask on Port #2.
DeviceRemovable:
Each bit is dedicated to a port of the Root
Hub. When cleared, the attached device is removable. When
set, the attached device is not removable.
15 to 0
DR[15:0]
Bit 0 —
reserved
Bit 1 —
Device attached to Port #1
Bit 2 —
Device attached to Port #2.
Table 82:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhStatus register: bit allocation
31
CRWE
0
R/W
23
30
29
28
27
26
25
24
reserved
0
-
19
0
-
0
-
0
-
0
-
0
-
0
-
22
21
20
18
17
16
reserved
CCIC
0
R/W
9
LPSC
0
R/W
8
0
-
0
-
0
-
0
-
0
-
0
-
15
14
13
12
11
10
DRWE
0
R/W
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
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